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參數(shù)資料
| 型號： | AK4682EQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Multi-channel CODEC with 2Vrms Stereo Selector |
| 中文描述： | 多通道選擇與2Vrms的立體聲編解碼器 |
| 文件頁數(shù)： | 33/43頁 |
| 文件大?。?/td> | 667K |
| 代理商： | AK4682EQ |
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[AK4682]
MS0610-E-01
2007/07
- 33 -
3. READ Operations
Set R/W bit = “1” for the READ operation of the AK4682.
After transmission of a data, the master can read next address’s data by generating the acknowledge instead of
terminating the write cycle after the receipt of the first data word. After the receipt of each data, the internal 5bits
address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds
0DH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The AK4682 supports two basic read operations: CURRENT ADDRESS READ and RANDOM READ.
3-1. CURRENT ADDRESS READ
The AK4682 contains an internal address counter that maintains the address of the last word accessed, incremented by
one. Therefore, if the last access (either a read or write) was to address “n”, the next CURRENT READ operation
would access data from the address “n+1”.
After receipt of the slave address with R/W bit set to “1”, the AK4682 generates an acknowledge, transmits 1byte data
which address is set by the internal address counter and increments the internal address counter by 1. If the master does
not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues transmission
S
T
A
R
T
SDA
A
C
K
A
C
K
S
Slave
Address
A
C
K
Data(n)
Data(n+1)
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+2)
Figure 21. CURRENT ADDRESS READ
3-2. RANDOM READ
Random read operation allows the master to access any memory location at random. Prior to issuing the slave address
with the R/W bit set to “1”, the master must first perform a “dummy” write operation.
The master issues the start condition, slave address(R/W=“0”) and then the register address to read. After the register
address’s acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to
“1”. Then the AK4682 generates an acknowledge, 1byte data and increments the internal address counter by 1. If the
master does not generate an acknowledge to the data but generate the stop condition, the AK4682 discontinues
transmission.
S
T
A
R
T
T
SDA
A
C
K
A
C
K
S
S
S
T
A
R
Slave
Address
Word
Address(n)
Slave
Address
A
C
K
Data(n)
A
C
K
P
S
T
O
P
Data(n+x)
A
C
K
Data(n+1)
Figure 22. RANDOM READ
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4683_07 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4702EQ | 2ch DAC with AV SCART switch |
| AK4702 | 2CH DAC WITH AV SCART SWITCH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4683 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_07 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_10 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQP | 制造商:AKM Semiconductor Inc 功能描述:Audio Codec 2ADC / 4DAC 24-Bit 64-Pin LQFP |
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