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參數(shù)資料
| 型號： | AK4682EQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Multi-channel CODEC with 2Vrms Stereo Selector |
| 中文描述： | 多通道選擇與2Vrms的立體聲編解碼器 |
| 文件頁數(shù)： | 14/43頁 |
| 文件大小： | 667K |
| 代理商： | AK4682EQ |
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[AK4682]
MS0610-E-01
2007/07
- 14 -
OPERATION OVERVIEW
■
System Clock
The AK4682 has two audio serial interface (PORTA, PORTB) can operate asynchronously. At each PORT, the external
clocks, which are required to operate the AK4682, are MCLKA (MCLKB), LRCKA (LRCKB) and BICKA (BICKB).
The MCLKA (MCLKB) must be synchronized with LRCKA (LRCKB) but the phase is not critical. The PORT A is the
audio data interface for DAC and the PORTB is for ADC.
■
Master/Slave Mode
The MSB pin and MSB bit are internally ORed and select the master/slave mode of PORTB. PORTA is slave mode only.
In master mode, LRCKB pin and BICKB pin are output pins. In slave mode, LRCKA (LRCKB) pin and BICKA
(BICKB) pin are input (Table 1).
The AK4682 is slave mode at power-down (PDN pin = “L”). To change to the master mode, set MSB pin “H” or write
“1” to MSB bit. Until when setting MSB pin “H” or writing “1” to MSB bit, LRCKB and BICKB pins are input pins.
Pull-up (or down) resistor with around 100kohm is required to prevent the floating of these input pins.
MSB bit
(default: “0”)
L
x
L
H
x
Output “L”(master mode)
L
0
L
1
H
H
x
PDN pin
MSB pin
PORTB (ADC)
BICKB, LRCKB
Input (slave mode)
PORTA (DAC)
BICKA, LRCKA
Input (slave mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
Input (slave mode)
(x: Don’t care)
Input (slave mode)
Output (master mode)
Output (master mode)
Table 1. Master/Salve Mode
■
ADC Clock Control
In master mode (MSB bit = “1”), the CKSB1-0 bits select the clock frequency (Table 2). The external clock (MCLKB)
must always be supplied except in the power-down mode. The ADC is in power-down mode until MCLKB is supplied.
CKSB1
CKSB0
0
0
0
1
1
0
1
1
Table 2. PORTB Master Clock Control (ADC Master Mode)
In slave mode (MSB bit = “0”. default), external clocks (MCLKB, BICKB, LRCKB) must always be present whenever
the ADC is in normal operation mode (PDN pin = “H” and PWAD = “1”). The master clock (MCLKB) must be
synchronized with LRCKB but the phase is not critical. If these clocks are not provided, the ADC may draw excess
current because the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC
must be in the power-down mode (PDN pin = “L” or PWAD = “0”) or in the reset mode (RSTN bit = “0”). After
exiting reset at power-up etc., the ADC is in the power-down mode until MCLKB and LRCKB are input.
Clock Speed
256fs
384fs
512fs
768fs
(default)
相關PDF資料 |
PDF描述 |
|---|---|
| AK4683_07 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4702EQ | 2ch DAC with AV SCART switch |
| AK4702 | 2CH DAC WITH AV SCART SWITCH |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4683 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_07 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_10 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQP | 制造商:AKM Semiconductor Inc 功能描述:Audio Codec 2ADC / 4DAC 24-Bit 64-Pin LQFP |
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