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參數(shù)資料
| 型號： | AK4682EQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Multi-channel CODEC with 2Vrms Stereo Selector |
| 中文描述： | 多通道選擇與2Vrms的立體聲編解碼器 |
| 文件頁數(shù)： | 15/43頁 |
| 文件大?。?/td> | 667K |
| 代理商： | AK4682EQ |
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[AK4682]
MS0610-E-01
2007/07
- 15 -
LRCKB
fs
32.0kHz
44.1kHz
48.0kHz
MCLKB (MHz)
256fs
8.1920
11.2896
12.2880
128fs
-
-
-
192fs
-
-
-
384fs
12.2880
16.9344
18.4320
512fs
16.3840
22.5792
24.5760
768fs
24.5760
33.8688
36.8640
Sampling
Speed
Normal
Table 3. System clock example (ADC Slave Mode)
■
DAC Clock Control
External clocks (MCLKA, BICKA, LRCKA) must always be present whenever the DAC is in normal operation mode
(PDN pin = “H” and PWDA = “1”). The master clock (MCLKA) must be synchronized with LRCKA but the phase is
not critical. If these clocks are not provided, the DAC may draw excess current because the device utilizes dynamic
refreshed logic internally. If the external clocks are not present, the DAC must be in the power-down mode (PDN pin =
“L” or PWDA = “0”) or in the reset mode (RSTN bit = “0”). After exiting reset at power-up etc., the DAC is in the
power-down mode until MCLKA and LRCKA are input.
There are two modes for controlling the sampling speed of DAC. One is the Manual Setting Mode (ACKS bit = “0”)
using the DFS1-0 bits, and the other is Auto Setting Mode (ACKS bit = “1”).
1. Manual Setting Mode (ACKS bit = “0”)
When the ACKS bit = “0”, DAC is in Manual Setting Mode and the sampling speed is selected by DFS1-0 bits (Table
4).
DFS1
0
0
1
1
DFS0
0
1
0
1
DAC Sampling Speed (fs)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Not Available
(Note: ADC is always in Normal Speed Mode)
Table 4.DAC sampling speed (ACKS bit = “0”, Manual Setting Mode)
32kHz~48kHz
64kHz~96kHz
120kHz~192kHz
-
(default)
LRCKA
fs
32.0kHz
44.1kHz
48.0kHz
MCLKA (MHz)
384fs
12.2880
16.9344
18.4320
BICKA (MHz)
64fs
2.0480
2.8224
3.0720
256fs
8.1920
11.2896
12.2880
512fs
16.3840
22.5792
24.5760
768fs
24.5760
33.8688
36.8640
Table 5. DAC system clock example (DAC Normal Speed Mode @Manual Setting Mode)
LRCKA
MCLKA (MHz)
fs
128fs
192fs
88.2kHz
11.2896
16.9344
96.0kHz
12.2880
18.4320
Table 6. DAC system clock example(DAC Double Speed Mode @Manual Setting Mode)
BICKA (MHz)
64fs
5.6448
6.1440
256fs
22.5792
24.5760
384fs
33.8688
36.8640
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4683_07 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4702EQ | 2ch DAC with AV SCART switch |
| AK4702 | 2CH DAC WITH AV SCART SWITCH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4683 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_07 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_10 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQP | 制造商:AKM Semiconductor Inc 功能描述:Audio Codec 2ADC / 4DAC 24-Bit 64-Pin LQFP |
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