參數(shù)資料
型號： AK4682EQ
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： Multi-channel CODEC with 2Vrms Stereo Selector
中文描述： 多通道選擇與2Vrms的立體聲編解碼器
文件頁數(shù)： 28/43頁
文件大?。?/td> 667K
代理商： AK4682EQ
[AK4682]
MS0610-E-01
2007/07
- 28 -
■
Power ON/OFF Sequence
The each block of the AK4682 are placed in the power-down mode by bringing PDN pin “L” and both digital filters are
reset at the same time. PDN pin “L” also reset the control registers to their default values. In the power-down mode, the
DAC outputs go to AVDD2 voltage and SDTOB pin goes to “L”. This reset must always be done after power-up.
In slave mode, after exiting reset at power-up etc., the DAC (ADC) starts to operate from the rising edge of LRCKA
(LRCKB) after MLCKA (MCLKB), and then the device is in the power-down mode until MCLKA (MCLKB) and
LRCKA (LRCKB) are input. In slave mode, the DAC (ADC) starts to operate by the input of MLCKA (MCLKB) after
exiting reset.
The analog initialization cycle of ADC starts after exiting the power-down mode. Therefore, the output data, SDTOB
becomes available after 522/fs cycles of LRCKB clock. In case of the DAC, an analog initialization cycle starts after
exiting the power-down mode. The analog outputs are AVDD2 voltage during the initialization. Figure 12 shows the
sequences of the power-down and the power-up.
The ADC and all DACs can be powered-down individually by PWAD and PWDA bits. These bits don’t initialize the
internal register values. When PWAD bit = “0”, the SDTOB pin goes to “L”. When PWDA bit = “0”, the DAC outputs
go to AVDD2 voltage. Since some click noise may occur, the analog output should muted externally if the click noise
influences system application.
Power
ADC Internal
State
PDN
Clock In
MCLK,LRCK,SCLK
ADC In
(Analog)
ADC Out
(Digital)
DAC Internal
State
DAC In
(Digital)
DAC Out
(Analog)
External
Mute
Mute ON
(8)
Power-down
Don’t care
GD
“0”data
Power-down
“0”data
GD
(3)
(3)
(4)
(6)
(7)
522/fs
Init Cycle
Normal Operation
(1)
GD
Normal Operation
GD
(5)
(6)
516/fs
Init Cycle
(2)
Mute ON
“0”data
“0”data
Don’t care
(6)
Notes:
(1) The analog part of ADC is initialized after exiting the power-down state.
(2) The analog part of DAC is initialized after exiting the power-down state.
(3) Digital output corresponding to analog input and analog output corresponding to digital input have the group
delay (GD).
(4) ADC output is “0” data at the power-down state.
(5) Click noise occurs at the end of initialization of the analog part. Please mute the digital output externally if the
click noise influences system application.
(6) Click noise occurs at the rising/falling edge of PDN and at 512/fs after the rising edge of PDN.
(7) When the external clocks
(MCLKA (MCLKB), BICKA (BICKB), and LRCKA (LRCKB))
are stopped, the AK4682
must be in the power-down mode.
(8) Please mute the analog output externally if the click noise (6) influences system application.
Figure 12. Power-down/up sequence example
相關(guān)PDF資料
PDF描述
AK4683_07 Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683EQ Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683 Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4702EQ 2ch DAC with AV SCART switch
AK4702 2CH DAC WITH AV SCART SWITCH
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4683 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683_07 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683_10 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683EQ 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T
AK4683EQP 制造商:AKM Semiconductor Inc 功能描述:Audio Codec 2ADC / 4DAC 24-Bit 64-Pin LQFP
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