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參數(shù)資料
| 型號(hào)： | AK4682EQ |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | Multi-channel CODEC with 2Vrms Stereo Selector |
| 中文描述： | 多通道選擇與2Vrms的立體聲編解碼器 |
| 文件頁(yè)數(shù)： | 10/43頁(yè) |
| 文件大小： | 667K |
| 代理商： | AK4682EQ |
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[AK4682]
MS0610-E-01
2007/07
- 10 -
Parameter
Audio Interface Timing (Slave Mode)
Normal mode(PORTA)
BICKA Period
BICKA Pulse Width Low
Pulse Width High
LRCKA Edge to BICKA “
↑
” (Note: 13)
BICKA “
↑
” to LRCKA Edge (Note: 13)
SDTIA1-2 Hold Time
SDTIA1-2 Setup Time
Normal mode(PORTB)
BICKB Period
BICKB Pulse Width Low
Pulse Width High
LRCKB Edge to BICKB “
↑
” (Note: 13)
BICKB “
↑
” to LRCKB Edge (Note: 13)
LRCKB to SDTOB (MSB)
BICKB “
↓
” to SDTOB
TDM 128 mode
BICKA Period
BICKA Pulse Width Low
Pulse Width High
LRCKA Edge to BICKA “
↑
” (Note: 13)
BICKA “
↑
” to LRCKA Edge (Note: 13)
SDTIA1-2 Hold Time
SDTIA1-2 Setup Time
Audio Interface Timing (Master Mode)
Normal mode
BICKB Frequency
BICKB Duty
BICKB “
↓
” to LRCKB Edge
BICKB “
↓
” to SDTO
Control Interface Timing (I
2
C Bus):
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time
(prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note: 14)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed by Input Filter
Capacitive load on bus
Note: 13 BICK rising edge must not occur at the same time as LRCK edge.
Note: 14 Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 15 I
2
C is a registered trademark of Philips Semiconductors.
Symbol
min
81
32
32
20
20
10
10
324
128
128
80
80
81
32
32
20
20
10
10
-40
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
-
0
typ
max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
80
80
tBCK
tBCKL
tBCKH
tLRB
tBLR
tSDH
tSDS
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
kHz
μ
s
μ
s
fBCK
dBCK
tMBLR
tBSD
64fs
50
40
20
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tSP
Cb
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
pF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4683_07 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683 | Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4702EQ | 2ch DAC with AV SCART switch |
| AK4702 | 2CH DAC WITH AV SCART SWITCH |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4683 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_07 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683_10 | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQ | 制造商:AKM 制造商全稱:AKM 功能描述:Asynchronous Multi-Channel Audio CODEC with DIR/T |
| AK4683EQP | 制造商:AKM Semiconductor Inc 功能描述:Audio Codec 2ADC / 4DAC 24-Bit 64-Pin LQFP |
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