
[AK4645EZ]
MS0605-E-00
2007/06
- 82 -
SYSTEM DESIGN
Figure 73 and Figure 74 shows the system connection diagram for the AK4645. An evaluation board [AKD4645] is
available which demonstrates the optimum layout, power supply arrangements and measurement results.
LIN4
ROUT
LOUT
MIN
RIN2
LIN2
LIN1
RIN1
R
M
H
H
H
H
M
M
M
V
A
A
V
I
P
C
TVDD
DVDD
BICK
LRCK
SDTO
SDTI
CDTI
CCLK
AK4645EZ
Top View
25
26
27
28
29
30
31
32
2
2
2
1
16
15
14
13
12
11
10
9
2
2
1
1
1
2
3
4
5
6
7
8
2
2
2
2
External MIC
Internal MIC
1u
0
2
0
R
6
4
6
4
10
0.22u
10
0.22u
Power Supply
2.6
~
3.6V
0
0.1u
1
DSP
μ
P
Speaker
Headphone
Mono In
Cp
10u
Analog Ground
Digital Ground
Power Supply
1.6
~
3.6V
0.1u
Line In
External
SPK-Amp
Notes:
- AVSS and HVSS of the AK4645 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK4645 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC/RIN3 pin is not needed.
- When the AK4645 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC/RIN3 pin should be
connected as shown in Table 5.
- When the AK4645 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100k
Ω
around pull-up resistor should be connected to LRCK and BICK pins of the AK4645.
- 0.1
μ
F ceramic capacitor should be attached to each supply pins. The type of other capacitors is not critical.
- When DVDD is supplied from AVDD via 10
Ω
series resistor, the capacitor larger than 0.1
μ
F should not be
connected between DVDD and the ground.
Figure 73. Typical Connection Diagram (AIN3 bit = “0”, MIC Input)