
[AK4645EZ]
MS0605-E-00
2007/06
- 73 -
Addr
03H
Register Name
Signal Select 2
Default
D7
LOVL
0
D6
LOPS
0
D5
D4
0
0
D3
0
0
D2
MINL
0
D1
0
0
D0
0
0
MGAIN1
0
MINL: Switch Control from MIN pin to Stereo Line Output
0: OFF (Default)
1: ON
When PMLO bit is “1”, MINL bit is enabled. When PMLO bit is “0”, the LOUT/ROUT pins go to AVSS.
MGAIN1: MIC-Amp Gain Control (Table 23)
LOPS: Stereo Line Output Power-Save Mode
0: Normal Operation (Default)
1: Power-Save Mode
LOVL: Stereo Line Output Gain Select (Table 51 and Table 53)
0: 0dB/+6dB (Default)
1: +2dB/+8dB
Addr
Register Name
D7
D6
04H
Mode Control 1
PLL3
PLL2
Default
0
0
DIF1-0: Audio Interface Format (Table 17)
Default: “10” (Left jutified)
BCKO: BICK Output Frequency Select at Master Mode (Table 11)
PLL3-0: PLL Reference Clock Select (Table 5)
Default: “0000” (LRCK pin)
Addr
Register Name
D7
D6
05H
Mode Control 2
PS1
PS0
Default
0
0
FS3-0: Sampling Frequency Select (Table 6 and Table 7) and MCKI Frequency Select (Table 12)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKP: BICK Polarity at DSP Mode (Table 18)
“0”: SDTO is output by the rising edge (“
↑
”) of BICK and SDTI is latched by the falling edge (“
↓
”). (Default)
“1”: SDTO is output by the falling edge (“
↓
”) of BICK and SDTI is latched by the rising edge (“
↑
”).
MSBS: LRCK Polarity at DSP Mode (Table 18)
“0”: The rising edge (“
↑
”) of LRCK is half clock of BICK before the channel change. (Default)
“1”: The rising edge (“
↑
”) of LRCK is one clock of BICK before the channel change.
PS1-0: MCKO Output Frequency Select (Table 10)
Default: “00” (256fs)
D5
PLL1
0
D4
PLL0
0
D3
D2
0
0
D1
DIF1
1
D0
DIF0
0
BCKO
0
D5
FS3
0
D4
MSBS
0
D3
BCKP
0
D2
FS2
0
D1
FS1
0
D0
FS0
0