
[AK4645EZ]
MS0605-E-00
2007/06
- 16 -
Parameter
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN Edge to CCLK “
↑
” (Note 34)
CCLK “
↑
” to CSN Edge (Note 34)
Control Interface Timing (I
2
C Bus mode):
(Note 33)
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 35)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
Power-down & Reset Timing
PDN Pulse Width (Note 36)
PMADL or PMADR “
↑
” to SDTO valid (Note 37)
Note 33. I
2
C is a registered trademark of Philips Semiconductors.
Note 34. CCLK rising edge must not occur at the same time as CSN edge.
Note 35. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 36. The AK4645 can be reset by the PDN pin = “L”.
Note 37. This is the count of LRCK “
↑
” from the PMADL or PMADR bit = “1”.
Symbol
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
Cb
tSP
tPD
tPDV
min
200
80
80
40
40
150
50
50
-
1.3
0.6
1.3
0.6
0.6
0
0.1
-
-
0.6
-
0
150
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1059
max
-
-
-
-
-
-
-
-
400
-
-
-
-
-
-
-
0.3
0.3
-
400
50
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
pF
ns
ns
1/fs