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參數(shù)資料
| 型號： | AK4620A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| 中文描述： | 24位192kHz的音頻編解碼器單親遺傳算法 |
| 文件頁數(shù)： | 25/42頁 |
| 文件大?。?/td> | 395K |
| 代理商： | AK4620A |
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ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 25 -
ADC Single-ended/Differential Input Mode
The ADC has a selectable single-ended or differential input mode. This mode can be selected by ADMODE pin, AML bit
and AMR bit. (See Table 15 and Table 16) In differential input mode, the IPGA is powered-down and bypassed. IATT
can be controlled in differential mode.
ADMODE pin
Lch
L
Single-ended
H
Differential
Table 15. ADC Input Mode in parallel mode
ADMODE pin
AML bit
AMR bit
0
0
0
1
1
0
1
1
H
X
X
Table 16. ADC Input Mode in serial mode (X: Don’t care)
Soft Mute Operation
Soft mute operation is performed in the digital domain of the DAC input. When the SMUTE bit goes to “1”, the output
signal is attenuated by
∞
during ATT_DATA
×
ATT transition time (Table 12) from the current ATT level. When
SMUTE bit is returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during
ATT_DATA
×
ATT transition time. If soft mute is cancelled before attenuating to
∞
after starting the operation, the
attenuation is discontinued and returns to ATT level by the same cycle. The soft mute is effective for changing the signal
source without stopping the signal transmission.
SMUTE bit
Rch
Single-ended
Differential
Lch
Rch
Single-ended
Single-ended
Differential
Differential
Differential
Single-ended
Differential
Single-ended
Differential
Differential
L
Attenuation
DZF pin
ATT_Level
-
∞
AOUT
8192/fs
GD
(2)
GD
(2)
(1)
(3)
(4)
(1)
Notes:
(1) ATT_DATA
×
ATT transition time (Table 12). For example, this time is 1020LRCK cycles (1020/fs)
at ATT_DATA=255 in Normal Speed Mode.
(2) Analog output corresponding to digital input has group delay (GD).
(3) If the soft mute is cancelled before attenuating
∞
after starting the operation, the attenuation is discontinued
and returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zero for 8192 LRCK cycles, DZF pin of each channel goes
to “H”. DZF pin immediately goes to “L” if input data are not zero after going DZF pin “H”.
Figure 10. Soft Mute and Zero Detection
相關PDF資料 |
PDF描述 |
|---|---|
| AK4620AVF | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620B | 24-Bit 192kHz Audio CODEC with IPGA |
| AK4620BVF | 24-Bit 192kHz Audio CODEC with IPGA |
| AK4626A | High Performance Multi-channel Audio CODEC |
| AK4626AVQ | High Performance Multi-channel Audio CODEC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AK4620AVF | 制造商:AKM 制造商全稱:AKM 功能描述:24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620AVFP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4620B | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 192kHz Audio CODEC with IPGA |
| AK4620BVF | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 192kHz Audio CODEC with IPGA |
| AK4620BVFPE2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
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