
ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 12 -
DIGITAL CHARACTERISTICS
(Ta=25
°
C; VA=4.75
~
5.25V; VD=3.0
~
3.6V, VT=3.0
~
5.25V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage (Iout=-100
μ
A)
Low-Level Output Voltage (Iout=100
μ
A)
Input Leakage Current
Symbol
VIH
VIL
VOH
VOL
Iin
min
70%VD
-
VD-0.5
-
-
typ
-
-
-
-
-
max
VT
30%VD
-
0.5
±
10
Units
V
V
V
V
μ
A
SWITCHING CHARACTERISTICS
(Ta=25
°
C; VA=4.75
~
5.25V; VD=3.0
~
3.6V, VT=3.0
~
5.25V; C
L
=20pF)
Parameter
Master Clock Timing
Frequency
Pulse Width Low
Pulse Width High
Symbol
fCLK
tCLKL
tCLKH
min
8.192
0.4/fCLK
0.4/fCLK
typ
max
55.296
Units
MHz
ns
ns
LRCK Frequency
(Note 22)
Normal Speed Mode (DFS0=“0”, DFS1=”0”)
Double Speed Mode (DFS0=“1”, DFS1=”0”)
Quad Speed Mode (DFS0=“0”, DFS1=”1”)
Duty Cycle
fsn
fsd
fsq
32
54
108
45
54
108
216
55
kHz
kHz
kHz
%
PCM Audio Interface Timing
BICK Period
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑
” (Note 23)
BICK “
↑
” to LRCK Edge (Note 23)
LRCK to SDTO (MSB) (Except I
2
S mode)
BICK “
↓
” to SDTO
SDTI Hold Time
SDTI Setup Time
DSD Audio Interface Timing
DCLK Period
DCLK Pulse Width Low
Pulse Width High
DCLK Edge to DSDL/R (Note 24)
Note 22. When the normal/double/quad speed modes are switched, the AK4620A should be reset by PDN pin or RSTN
bit.
Note 23. BICK rising edge must not occur at the same time as LRCK edge.
Note 24. DSD data transmitting device must meet this time.
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRS
tBSD
tSDH
tSDS
tDCK
tDCKL
tDCKH
tDDD
1/128fsn
1/64fsd
1/64fsq
33
33
20
20
20
20
1/64fs
160
160
-20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns