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參數(shù)資料
| 型號(hào)： | AK4620A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| 中文描述： | 24位192kHz的音頻編解碼器單親遺傳算法 |
| 文件頁數(shù)： | 19/42頁 |
| 文件大?。?/td> | 395K |
| 代理商： | AK4620A |
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ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 19 -
MCLK (Normal speed)
256fs
512fs
1024fs
384fs
768fs
fs=44.1kHz
11.2896MHz 12.288MHz
22.5792MHz 24.576MHz
45.1584MHz 49.152MHz
16.9344MHz 18.432MHz
33.8688MHz 36.864MHz
fs=48kHz
MCLK (Double speed)
N/A
256fs
512fs
N/A
384fs
fs=88.2kHz
N/A
22.5792MHz 24.576MHz
45.1584MHz 49.152MHz
N/A
33.8688MHz 36.864MHz
fs=96kHz
N/A
N/A
MCLK (Quad speed)
128fs
256fs
192fs
fs=176.4kHz
22.5792MHz
45.1584MHz
33.8688MHz
fs=192kHz
24.576MHz
49.152MHz
36.864MHz
Table 8. Master clock frequency example
2. DSD Mode
The external clocks, which are required to operate the AK4620A, are MCLK and DCLK. The master clock (MCLK)
should be synchronized with DSD clock (DCLK) but the phase is not critical. The frequency of MCLK is set by DCKS
bit.
All external clocks (MCLK, DCLK) must be present whenever the AK4620A is in the normal operation mode (PDN pin
= “H”). If these clocks are not provided, the AK4620A may draw excess current because the device utilizes dynamically
refreshed logic. The AK4620A should be reset by PDN pin = “L” after these clocks are provided. If the external clocks
are not present, the AK4620A should be in the power-down mode (PDN pin = “L”). After exiting reset (PDN pin = “
↑
”)
at power-up etc., the AK4620A is in the power-down mode until MCLK is provided.
Audio Serial Interface Format
1. PCM Mode
Five serial modes are supported and selected by the DIF2-0 bits in Serial Mode (two modes by DIF pin in Parallel Mode)
as shown in Table 9 and Table 10. In all modes the serial data has MSB first, 2’s complement format. The SDTO is
clocked out on the falling edge of BICK and the SDTI is latched on the rising edge. Mode2 can be used for 20 and 16
MSB justified formats by zeroing the unused LSBs.
Mode
DIF2
DIF1
DIF0
SDTO
0
0
0
0
24bit, MSB justified
1
0
0
1
24bit, MSB justified
2
0
1
0
24bit, MSB justified
3
0
1
1
24bit, I
2
S
4
1
0
0
24bit, MSB justified
Table 9. Audio data format (Serial Mode)
Mode
DIF pin
SDTO
2
L
24bit, MSB justified
24bit, MSB justified
3
H
24bit, I
2
S
Table 10. Audio data format (Parallel Mode)
SDTI
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
≥
48fs
≥
48fs
≥
48fs Default
≥
48fs
≥
48fs
16bit, LSB justified
20bit, LSB justified
24bit, MSB justified
24bit, I
2
S
24bit, LSB justified
SDTI
LRCK
H/L
L/H
BICK
≥
48fs
≥
48fs
24bit, I
2
S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4620AVF | 24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620B | 24-Bit 192kHz Audio CODEC with IPGA |
| AK4620BVF | 24-Bit 192kHz Audio CODEC with IPGA |
| AK4626A | High Performance Multi-channel Audio CODEC |
| AK4626AVQ | High Performance Multi-channel Audio CODEC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4620AVF | 制造商:AKM 制造商全稱:AKM 功能描述:24 BIT 192KHZ AUDIO CODEC WITH IPGA |
| AK4620AVFP-E2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4620B | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 192kHz Audio CODEC with IPGA |
| AK4620BVF | 制造商:AKM 制造商全稱:AKM 功能描述:24-Bit 192kHz Audio CODEC with IPGA |
| AK4620BVFPE2 | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
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