
ASAHI KASEI
[AK4620A]
MS0368-E-00
2004/12
- 18 -
CMODE bit
CKS1 bit
CKS0 bit
MCLK
Normal Speed
(DFS1-0 = “00”)
256fs
512fs
1024fs
N/A
384fs
768fs
MCLK
Double Speed
(DFS1-0 = “01”)
N/A
256fs
512fs
Auto Setting Mode (*)
N/A
384fs
MCLK
Quad Speed
(DFS1-0 = “10”)
N/A
128fs
256fs
N/A
N/A
192fs
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Default
Table 3. Master clock frequency in serial mode (“*”: refer to Table 4)
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.
MCLK/LRCK ratio
512 or 768
256 or 384
128 or 192
Mode
Sampling Rate
32kHz-54kHz
54kHz-108kHz
108kHz-216kHz
Normal speed
Double speed
Quad speed
Table 4. Auto Setting Mode in serial mode (DFS1-0 = “01”, CMODE bit = “1”, CKS1-0 bit = “11”)
1-2. Parallel mode (P/S pin= “H”)
As shown in Table 5, Table 6 and Table 7, select the MCLK frequency with the CKS0-1 and DFS0 pins. These
pins should be changed when the PDN pin = “L”.
DFS0 pin
L
H
Mode
Sampling Rate
32kHz-54kHz
54kHz-108kHz
Normal speed
Double speed
Table 5. Sampling speed in parallel mode
CKS1 pin
CKS0 pin
MCLK
Normal Speed
(DFS0 pin = “L”)
256fs
512fs
384fs
1024fs
MCLK
Double Speed
(DFS0 pin = “H”)
N/A
256fs
Auto Setting Mode (*)
512fs
L
L
H
H
L
H
L
H
Table 6. Master clock frequency in parallel mode (“*”; refer to Table 7.)
The Auto Setting Mode detects MCLK/LRCK ratio and selects Normal/Double/Quad speed mode automatically.
MCLK/LRCK ratio
512 or 768
256 or 384
128 or 192
Mode
Sampling Rate
32kHz-54kHz
54kHz-108kHz
108kHz-216kHz
Normal speed
Double speed
Quad speed
Table 7. Auto Setting Mode in parallel mode (DFS0 pin = “H”, CKS1 pin = “H”, CKS0 pin = “L”)