
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 65 -
4. When an external clock is used in PLL mode. (Master mode)
MCKPD bit
(Addr:01H, D7)
PS1-0 bits
(Addr:04H, D5-4)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
XX
00
40ms(max)
Output
BICK, LRCK
(Master Mode)
Output
External MCLK
Input
(1)
(2)
(3)
(4)
(5)
Example :
Audio I/F Format : I
2
S
BICK frequency at Master Mode : 64fs
Input Master Clock Select at PLL Mode : 11.2896MHz
Output Master Clock Frequency : 64fs
(1) Addr:01H, Data:00H
(2) Input external MCLK
(3) Addr:01H, Data 20H
(5) MCKO, BICK and LRCK output starts
(4) Addr:04H, Data 6AH
Figure 52. Clock Set Up Sequence(4)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1”
→
“0”
(2) Input an external MCLK
(3) Power-up PLL : PMPLL bit = “0”
→
“1”
PLL needs 40ms lock time after the PMPLL bit = “0”
→
“1”.
(4) Enable MCKO output : MCKO bit = “0”
→
“1” and set up MCKO output frequency (PS1-0 bits)
(5) MCKO, BICK and LRCK are output after PLL lock time.
5. External clock mode
MCKPD bit
(Addr:01H, D7)
FS1-0 bits
(Addr:05H, D6-5)
XX
00
BICK, LRCK
(Slave Mode)
Input
External MCLK
Input
BICK, LRCK
(Master Mode)
Output
(1)
(2)
(3)
(4)
(5)
Example :
Audio I/F Format : I
2
S
BICK frequency at Master Mode : 64fs
Input Master Clock Frequency : 256fs
(1) Addr:01H, Data:00H
(2) Addr:05H, Data 00H
(3) Input external MCLK
(4) Input BICK and LRCK(Slave)
(5) BICK and LRCK output(Master)
Figure 53. Clock Set Up Sequence(5)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1”
→
“0”
(2) Set up MCLK frequency (FS1-0 bits)
(3) Input an external MCLK
(4) In slave mode, input MCLK, BICK and LRCK.
(5) In master mode, while MCLK is input, BICK and LRCK are output.