參數(shù)資料
型號(hào)： AK4537VN
廠商： Asahi Kasei Microsystems Co.,Ltd
元件分類： Codec
英文描述： 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP
中文描述： 16位ツヒ立體聲編解碼器與麥克風(fēng)/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù)： 22/76頁
文件大?。?/td> 576K
代理商： AK4537VN
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 22 -
Master Mode (M/S pin = “H”)
Power down
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
BF bit = “0” : 64fs Output
BF bit = “1” : 32fs Output
Output
Table 5. Clock Operation at Master Mode (PLL Mode)
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
MCKI pin
Refer to Table 1
MCKO pin
“L”
BICK pin
“L”
“L”
LRCK pin
“L”
“L”
Slave Mode (M/S pin = “L”)
Power down
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
Input
Input
Table 6. Clock Operation at Slave Mode (PLL Mode)
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
Input
Input
MCKI pin
Refer to Table 1
MCKO pin
“L”
BICK pin
LRCK pin
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
(2) External mode (PMPLL bit = “0”)
When the PMPLL bit = “0”, the AK4537 works in external clock mode. The MCKO pin outputs a buffered clock of
MCKI input.
For example, when MCKI = 256fs, the sampling frequency is changeable from 8kHz to 48kHz (Table 7). The MCKO bit
controls MCKO output enable. The frequency of MCKO is selectable via register the PS1-0 bits as defined in Table 8.
If
PS1-0 bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after
LRCK is input in slave mode.
The master clock frequency should be changed only when the PMADL, PMADR and
PMDAC bits = “0”.
LRCK and BICK are output from the AK4537 in master mode. The clock to the MCKI pin must not stop during normal
operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If this clock is not provided, the AK4537 may
draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the
AK4537 in power-down mode (PMADL bit = PMADR bit = PMDAC bit = “0”).
MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with
sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present
whenever the AK4537 is in normal operation (PMADL bit = “1”, PMADR bit = “1” or PMDAC bit = “1”). If these clocks
are not provided, the AK4537 may draw excess current due to its use of internal dynamically refreshed logic. If the
external clocks are not present, place the AK4537 in power-down mode (PMADL bit = PMADR bit = PMDAC bit = “0”).
Mode
FS1
FS0
Sampling Frequency (fs)
0
0
0
1
0
1
2
1
0
3
1
1
Table 7. Sampling Frequency Select (EXT Mode)
MCKI
256fs
512fs
1024fs
N/A
Default
8kHz
～
48kHz
8kHz
～
24kHz
8kHz
～
12kHz
N/A
相關(guān)PDF資料
PDF描述
AK4538 16Bit DS CODEC with MIC/HP/SPK-AMP
AK4538VN 16Bit DS CODEC with MIC/HP/SPK-AMP
AK4541VQ AC’97 Rev 2.1 Multimedia Audio CODEC
AK4541 AC’97 Rev 2.1 Multimedia Audio CODEC
AK4543 AC’97 Rev 2.1 Multimedia Audio CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4537VNP-L 制造商:AKM Semiconductor Inc 功能描述:AK4537VNP-L
AK4538 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP
AK4538VN 制造商:AKM 制造商全稱:AKM 功能描述:16Bit DS CODEC with MIC/HP/SPK-AMP
AK4541 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
AK4541VQ 制造商:AKM 制造商全稱:AKM 功能描述:AC’97 Rev 2.1 Multimedia Audio CODEC
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