參數(shù)資料
型號: AK4537VN
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: 16-Bit ツヒ Stereo CODEC with MIC/HP/SPK-AMP
中文描述: 16位ツヒ立體聲編解碼器與麥克風/惠普/胰腎聯(lián)合移植腺苷
文件頁數(shù): 63/76頁
文件大?。?/td> 576K
代理商: AK4537VN
ASAHI KASEI
[AK4537]
MS0202-E-04
2005/04
- 63 -
2. When X'tal is used in PLL mode. (Master mode)
MCKPD bit
(Addr:01H, D7)
BICK, LRCK
(Master Mode)
PS1-0 bits
(Addr:04H, D5-4)
PMXTL bit
(Addr:01H, D6)
PMPLL bit
(Addr:01H, D5)
MCKO bit
(Addr:04H, D3)
MCKO pin
XX
00
40msec(max)
Output
Output
(1)
20ms(typ)(2)
(3)
(4)
E xam ple :
A udio I/F Fo rm at : I
2
S
B IC K freq ue ncy at M a ste r M o de : 64fs
Inp ut M aster C lo c k S e lect at P LL M o de : 1 1.2 896M H z
O utp ut M as ter C lo ck F re q ue ncy : 6 4fs
(1) A ddr:01H, D ata:40H
(2) A ddr:01H, D ata:60H
(3) A ddr:04H, D ata 6A H
(4) M CK O , BICK and LRC K output starts
Figure 50. Clock Set Up Sequence(2)
<Example>
(1) Release the pull-down of the XTI pin : MCKPD bit = “1”
“0” and and power-up the X’tal oscillator: PMXTL
bit = “0”
“1”
(2) Power-up PLL : PMPLL bit = “0”
“1”
The PLL should be powered-up after the X’tal oscillator becomes stable. It takes X’tal oscillator 20ms(typ) to
be stable after PMXTL bit=“1”. This time depends on X’tal. PLL needs 40ms lock time the PMPLL bit = “0”
“1”.
(3) Enable MCKO output : MCKO bit = “0”
“1” and set up MCKO output frequency (PS1-0 bits)
(4) MCKO, BICK and LRCK are output after PLL lock time.
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