
ASAHI KASEI
[AK4342]
MS0506-E-02
2006/07
- 24 -
Lineout amp
Power supply voltage for lineout amplifier is applied from HVDD and HVEE pins. HVEE pin must be connected with
PVEE pin directly. PVEE pin outputs the negative voltage generated by the internal charge pump circuit. The lineout
amplifiers are single-ended outputs and centered on 0V(HVSS). The output level is typically 2Vrms (@ AVDD=3.3V,
0dBFS). The minimum load resistance is 10k
.
1. Analog volume for lineout
These volumes are common to L/R channels and can attenuate the DAC output signal from +0dB to –31dB with 1dB step
(See Table 11). Changing levels don’t have any pop noise. The transition time is selected by PTS1-0 bits and sampling
frequency (See Table 2 and Table 15).
LPGA4-0 bits
ATT (dB)
1FH
0
1EH
-1
1DH
-2
1CH
-3
18H
-29
01H
-30
00H
-31
Table 11. Volume Setting for Lineout
2. Mute Function
When LMUTE bit is set to “1”, the lineout amplifiers (LOUT and ROUT pins) go to ground level (0V). This mute time
depends on the setting of PTS1-0 bits and sampling frequency(FS3-0 bits). This function is common to L/R channels.
When LMUTE bit is set to “0”, the outputs are in normal operation.
3. Power-up/down
Lineout amplifiers are powered-up/down by PMLO bit. The power-on/off time depends on the setting of PUT1-0 bits and
sampling frequency (FS3-0 bits). The power-up/down of lineout amplifiers should be done in the mute state (LMUTE bit
= “1”).
4. Output circuit
When LOUT/ROUT drives some capacitive load, a resistor should be added in series between LOUT/ROUT and
capacitive load. Figure 18 shows an example of 470
series resistor. In this case, LOUT/ROUT can drive capacitive load
up to 1nF.
Step
Level
Default
1dB
32
470
1n
LOUT/ROUT
Analog
Out
Figure 18. External 1
st
order LPF Circuit Example
(fc = 339kHz, gain = -0.06dB @ 40kHz)