參數(shù)資料
型號(hào)： AK4342EN
廠商： Asahi Kasei Microsystems Co.,Ltd
英文描述： 24-Bit Stereo DAC with HP-AMP & 2V Line-Out
中文描述： 24位立體聲DAC惠普腺苷
文件頁數(shù)： 11/43頁
文件大?。?/td> 580K
代理商： AK4342EN
ASAHI KASEI
[AK4342]
MS0506-E-02
2006/07
- 11 -
SWITCHING CHARACTERISTICS
(Ta=25
°
C; AVDD, DVDD, HVDD, PVDD=2.7
～
3.6V; TVDD=1.6
～
3.6V)
Parameter
Master Clock Timing (2.7V
≤
TVDD
≤
3.6V)
Half Speed Mode (512/768fs)
Normal Speed Mode (256/384/512/768fs)
Double Speed Mode (128/192/256/384fs)
Pulse Width Low
Pulse Width High
Master Clock Timing (1.6V
≤
TVDD < 2.7V)
Half Speed Mode (512/768fs)
Normal Speed Mode (256/384fs)
Double Speed Mode (128/192fs)
Pulse Width Low
Pulse Width High
LRCK Timing
Frequency
Half Speed Mode (DFS1-0 bits = “10”)
Normal Speed Mode (DFS1-0 bits = “00”)
Double Speed Mode (DFS1-0 bits = “01”)
Duty Cycle
Serial Interface Timing
(Note 25)
BICK Period
Half Speed Mode
Normal Speed Mode
Double Speed Mode
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “
↑
”
(Note 26)
BICK “
↑
” to LRCK Edge
(Note 26)
LRCK Edge to BICK “
↓
”
(Note 27)
BICK “
↓
” to LRCK Edge
(Note 27)
SDATA Hold Time
SDATA Setup Time
Control Interface Timing (3-wire Serial mode)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “
↓
” to CCLK “
↑
”
CCLK “
↑
” to CSN “
↑
”
Power-down & Reset Timing
PDN Pulse Width
Note 25. Refer to “Serial Data Interface”.
Note 26. When BCKP bit is set to “0”, BICK rising edge must not occur at the same time as LRCK edge.
Note 27. When BCKP bit is set to “1”, BICK falling edge must not occur at the same time as LRCK edge.
Note 28. The AK4342 can be reset by bringing PDN pin = “L” to “H” only upon power up.
Symbol
fCLK
fCLK
fCLK
tCLKL
tCLKH
fCLK
fCLK
fCLK
tCLKL
tCLKH
fsh
fsn
fsd
Duty
tBCK
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRB
tBLR
tSDH
tSDS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tPD
min
4.096
2.048
6.144
0.4/fCLK
0.4/fCLK
4.096
2.048
6.144
0.4/fCLK
0.4/fCLK
8
8
60
45
1/128fsh
1/128fsn
1/64fsd
70
70
40
40
40
40
40
40
200
80
80
40
40
150
50
50
150
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
18.432
36.864
36.864
-
-
18.432
18.432
18.432
-
-
24
48
96
55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
MHz
MHz
MHz
ns
ns
MHz
MHz
MHz
ns
ns
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 28)
相關(guān)PDF資料
PDF描述
AK4343 Stereo DAC with HP/RCV/SPK-AMP
AK4343EN Stereo DAC with HP/RCV/SPK-AMP
AK4345 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
AK4345ET 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT
AK4346 3.3V 192kHz 24-Bit 6-Channel DAC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AK4342EN-L 制造商:ASAHI 功能描述:
AK4342ENP-L 制造商:Asahi Kasei Microsystems Co Ltd 功能描述:
AK4343 制造商:AKM 制造商全稱:AKM 功能描述:Stereo DAC with built-in HP/RCV/SPK amplifier
AK434-3 功能描述:CABLE CENTRONICS F-F 3M RoHS:否 類別:電纜組件 >> D形，Centronics 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 配置:VHDCI 68 位置公型至公型 長度:10.00'（3.05m） 纜線類型:圓形 - 黑色 屏蔽:屏蔽 樣式:SCSI Ultra 2
AK4343EN 制造商:AKM 制造商全稱:AKM 功能描述:Stereo DAC with HP/RCV/SPK-AMP
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