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參數(shù)資料
| 型號： | AK4342EN |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 英文描述： | 24-Bit Stereo DAC with HP-AMP & 2V Line-Out |
| 中文描述： | 24位立體聲DAC惠普腺苷 |
| 文件頁數(shù)： | 16/43頁 |
| 文件大?。?/td> | 580K |
| 代理商： | AK4342EN |
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ASAHI KASEI
[AK4342]
MS0506-E-02
2006/07
- 16 -
OPERATION OVERVIEW
System Clock
The external clocks required to operate the AK4342 are MCLK, BICK and LRCK. MCLK should be synchronized with
LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter, delta-sigma modulator,
charge pump circuit and counter for transition time. The MCLK frequency is detected from the relation between MCLK
and LRCK automatically. The Half speed, the Normal speed and the Double speed mode are selected with the DFS1-0
pins (Table 1). The sampling frequency is selected with the FS3-0 bits. (Table 2)
When the states of DFS1-0 bits change in the normal operation mode, the AK4342 should be reset by PDN pin or
PMDAC bit.
DFS1 bit
DFS0 bit
Mode
0
0
Normal Speed
8
～
48kHz
0
1
Double Speed
60
～
96kHz
1
0
Half Speed
8
～
24kHz
1
1
Table 1. System Clock Example
FS3 bit
FS2 bit
FS1 bit
FS0 bit
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Table 2. Set up of Sampling Frequency
For low sampling rates, DR and S/N degrade because of the out-of-band noise. DR and S/N are improved by setting the
half speed mode (DFS1-0 bits = “10”)
S/N (fs=8kHz, 20kLPF + A-weighted)
Mode
Lineout
Normal Speed
89dB
Half Speed
99dB
Table 3. Relationship between Clock Mode and S/N of Lineout, Headphone and Aux-out
External clocks (MCLK, BICK and LRCK) should always be present whenever the DAC, headphone amp, lineout amp or
charge pump circuits is in normal operation mode (PMDAC bit = “1”, PMHP bit = “1”, PMLO bit = “1” or PMCP bit =
“1”). If these clocks are not provided, the AK4342 is not operated normally, especially, DAC may draw excess current
due to dynamic refresh of internal logic. If the external clocks are not present, the DAC, headphone amp, charge pump
circuit and lineout amp should be in the power-down mode (PMDAC bit = PMHP bit = PMLO bit = PMCP bit = “0”).
fs
MCLK Frequency
256/384/512/768fs
128/192/256/384fs
512/768fs
Default
Reserve
Sampling Frequency
44.1kHz
32kHz
48kHz
(Reserve)
88.2kHz
64kHz
96kHz
(Reserve)
22.05kHz
16kHz
24kHz
(Reserve)
11.025kHz
8kHz
12kHz
(Reserve)
Default
Headphone
87dB
95dB
Aux-out
87dB
95dB
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AK4343 | Stereo DAC with HP/RCV/SPK-AMP |
| AK4343EN | Stereo DAC with HP/RCV/SPK-AMP |
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| AK4345ET | 100dB 96kHz 24-Bit Stereo 3.3V ツヒ DAC with DIT |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AK4342EN-L | 制造商:ASAHI 功能描述: |
| AK4342ENP-L | 制造商:Asahi Kasei Microsystems Co Ltd 功能描述: |
| AK4343 | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo DAC with built-in HP/RCV/SPK amplifier |
| AK434-3 | 功能描述:CABLE CENTRONICS F-F 3M RoHS:否 類別:電纜組件 >> D形，Centronics 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 配置:VHDCI 68 位置公型至公型 長度:10.00'（3.05m） 纜線類型:圓形 - 黑色 屏蔽:屏蔽 樣式:SCSI Ultra 2 |
| AK4343EN | 制造商:AKM 制造商全稱:AKM 功能描述:Stereo DAC with HP/RCV/SPK-AMP |
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