- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374047 > ADV7320 (Analog Devices, Inc.) Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs PDF資料下載
參數(shù)資料
| 型號： | ADV7320 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| 中文描述： | 多格式視頻編碼器216兆赫六噪聲整形的12位DAC |
| 文件頁數(shù)： | 61/88頁 |
| 文件大?。?/td> | 1002K |
| 代理商： | ADV7320 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁當(dāng)前第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
ADV7320/ADV7321
HSYNC/VSYNC OUTPUT CONTROL
Rev. 0 | Page 61 of 88
The ADV7320/21 has the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on
P_HSYNC/P_VSYNC, outputting the respective signals on the P_HSYNC and P_VSYNC pins.
Table 36. Hsync Output Control
1
HD/ED
2
Slave Mode
(0x10, bit 2)
x
x
HD/ED
Sync Out Enable
(0x02, Bit 7)
0
0
SD
Sync Out Enable
(0x02, Bit 6)
0
1
I2C_HSYNC _gen_sel
(0x14, Bit 1)
x
x
Signal on S_HSYNC Pin
Tristate
Pipelined SD HSYNC
Duration
–
See Appendix
5—SD Timing
Modes
As per HSYNC
timing
External HSYNC
& VSYNC/Field
Mode
EAV/SAV Mode
1
x
0
Pipelined Ext HD/ED HSYNC
1
x
0
Pipelined HD/ED HSYNC
based on AV code H bit
Pipelined HD/ED HSYNC
based on horizontal counter
Same as line
blanking interval
Same as
embedded
HSYNC
x
1
x
1
______________________________
1
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
2
ED = enhanced definition.
Table 37. VSYNC Output Control
1
HD/ED
2
Slave Mode
(0x10, Bit 2)
(0x02, Bit 7)
(0x02, Bit 6)
(0x14, Bit 2)
x
0
0
x
x
0
1
x
HD/ED
Sync out Enable
SD
Sync Out Enable
I2C_VSYNC _gen_sel
Video
Standard
x
Interlaced
Signal on
S_VSYNC Pin
Tristate
Pipelined SD
VSYNC/ field
Duration
-
See Appendix
5—SD Timing
Modes
As per Ext VSYNC
or field signal
External HSYNC
& VSYNC/Field
Mode
EAV/SAV Mode
1
x
0
x
Pipelined EXT
HD/ED VSYNC or
field signal
External pipelined
field signal based
on AV code F bit
Pipelined VSYNC
based on AV code
V bit
External pipelined
HD/ED VSYNC
based on vertical
counter
External pipelined
HD/ED VSYNC
based on vertical
counter
1
x
0
All HD interlace
standards
Field
EAV/SAV Mode
1
x
0
All HD/ED
progressive
standards
All HD/ED stan-
dards except
525p
Vertical blanking
interval
x
1
x
1
Aligned with
serration lines
x
1
x
1
525p
Vertical blanking
interval
1
In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.
2
ED = enhanced definition.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7321 | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| ADV7321KSTZ | Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs |
| ADV7324 | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| ADV7324KSTZ | Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs |
| ADV7340 | Multiformat Video Encoder, Six 12-Bit Noise Shaped Video㈢ DACS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV73205705 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73205706 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73205753 | 制造商:LG Corporation 功能描述:Frame Assembly |
| ADV73207202 | 制造商:LG Corporation 功能描述:Frame Assembly,Door |
| ADV73207203 | 制造商:LG Corporation 功能描述:FRAME ASSEMBLY,DOOR |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。