參數(shù)資料
型號： ADV7303AKST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： Sand Paper; Abrasive Grade:T; Color:White; Pack Quantity:3; Roll Length:30ft; Width:4"
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： PLASTIC, MS-026BCD, LQFP-64
文件頁數(shù)： 34/68頁
文件大?。?/td> 1177K
代理商： ADV7303AKST
REV. A
–34–
ADV7302A/ADV7303A
Table XIV. Truth Table
P_HSYNC
P_VSYNC
1
P_BLANK
1
Reference
2
1
→
0
0
0
→
1
1
1
0
0
→
1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0
0
→
1
1
→
0
50% point of falling edge of tri-level horizontal sync signal
25% point of rising edge of tri-level horizontal sync signal
50% point of falling edge of tri-level horizontal sync signal
50% start of active video
50% end of active video
a
b
c
d
e
NOTES
For standards that do not require a tri-sync level, P_BLANK must be tied low at all times.
1
When Async Timing Mode is enabled, P_BLANK, Pin 25 becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.
2
See Figure 28.
LCC1
GLL
P19–P12
ADV7185
VIDEO
DECODER
COMPOSITE
VIDEO
1
CLKIN_A
RTC_SCR_TR
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
S7–S0
RTC
LOW
COUNT START
128
TIME SLOT 01
13
0
14 BITS
RESERVED
14
21
19
F
SC
PLL INCREMENT
2
VALID
SAMPLE
INVALID
SAMPLE
8/LINE
LOCKED
CLOCK
6768
4 BITS
RESERVED
0
SEQUENCE
BIT
3
RESET
BIT
4
RESERVED
5 BITS
RESERVED
ADV7302A/
ADV7303A
NOTES
i.e., VCR OR CABLE
2
F
PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7302A/ADV7303A F
SC
DDS REGISTER IS F
PLL INCREMENTS BITS 21:0
PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7302A/ADV7303A.
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE
4
RESET ADV7302A/ADV7303A DDS
NOT USED
Figure 29. RTC Timing and Connections
SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]
In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync Control Bit can be used for
nonstandard input video, i.e., in Fast Forward or Rewind Modes.
In Fast Forward Mode, the sync information for the start of a
new field in the incoming video usually occurs before the total
number of lines/fields are reached; in Rewind Mode, this sync
signal occurs usually after the total number of lines/fields are
reached. Conventionally, this means that the output video will
have an erroneous start of new field signals, one generated by the
incoming video and one when the internal lines/field counters
reach the end of a field. When VCR FF/RW sync control is enabled
[Subaddress 42h, Bit 5] the lines/field counters are updated
according to the incoming VSYNC signal, and the analog output
matches the incoming VSYNC signal.
This control is available in all slave timing modes except Slave
Mode 0.
RESET SEQUENCE
A reset is activated with a high-to-low transition on the
RESET
Pin (Pin 33) according to the timing specifications. The
ADV7302A/ADV7303A will revert to the default output con-
figuration. Figure 30 illustrates the
RESET
sequence timing.
RESET
DIGITAL TIMING
OFF
DIGITAL TIMING SIGNALS SUPPRESSED
VALID VIDEO
TIMING ACTIVE
DACs
PIXEL DATA
VALID
Figure 30.
RESET
Timing Sequence
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