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參數(shù)資料
| 型號： | ADV7202 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Simultaneous Sampling Video Rate Codec |
| 中文描述： | 同時采樣率視頻編解碼器 |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 216K |
| 代理商： | ADV7202 |
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REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–9–
PIN FUNCTION DESCRIPTIONS
Input/
Output
I
Pin No.
1
Mnemonic
SYNC_IN
Function
This signal can be used to synchronize the updating of clamps. Polarity is pro-
grammable via I
2
C or SPI.
MPU Port Serial Interface Clock Input. If the SPI interface is enabled, this pin is
clock input. If the I
2
C interface is enabled, this pin is SCK.
If the SPI interface is enabled, this pin is Latch Enable. If the I
2
C interface is en-
abled, this pin is the ALSB Address Select Pin. This signal sets up the LSB of the
MPU address. MPU address = 2cH, ALSB = 0, MPU address = 2eH, ALSB = 1.
When this pin is tied high, the I
2
C filter is activated, which reduces noise on the
I
2
C interface. When this pin is tied low, the input bandwidth on the I
2
C lines is
increased.
Input Terminal for crystal oscillator or connection for external oscillator with
CMOS-compatible square wave clock signal.
Second Terminal for Crystal Oscillator. Not connected if external clock source
is used.
ADC Analog Supply Voltage (5 V or 3.3 V)
Ground for ADC Analog Supply
Analog Signal Inputs. Can be configured differentially or single-ended.
A high signal on the pin selects SPI MPU port serial operation; a low signal selects
I
2
C MPU port serial operation.
Internally generated Voltage Reference or programmable reference out.
Common-Mode Level for ADCs
ADC Capacitor Network
Enable data from OSDIN0–2 to be switched to the outputs when set to a logic high.
ADC data output
Third Input Channel for On-Screen Display
Second Input Channel for On-Screen Display
First Input Channel for On-Screen Display
General Purpose Analog Output
Analog Output. Can Be Used to Output CVBS, R or U
Ground for DAC Analog Supply
DAC Analog Supply Voltage (5 V or 3.3 V)
Analog Output. Can Be Used to Output CVBS, Y, G, or Luma.
Analog Output. Can Be Used to Output CVBS, V, B, or Chroma.
Compensation Pin for DACs. Connect 0.1
μ
F capacitor from COMP pin to
AVDD_DAC.
DAC Voltage Reference Output Pin, Nominally 1.235 V. Can be driven by an
external voltage reference.
Used to control the amplitude of the DAC output current, 1200
gives an I max
of 4.33
μ
A.
Master Reset (Asynchronous)
DAC Input Data for Four Video Rate DACs
2
CLK/SCK
I
3
LE/ALSB
I
4
XTAL0
I
5
XTAL1
O
6
7
8–19
20
AVDD_ADC
AVSS_ADC
AIN1–6
SPI_SEL
P
G
I
I
21
22
23, 24
25
26–35
36
37
38
39
40
41
42
43
44
45
REFADC
CML
CAP2, CAP1
OSDEN
DOUT[9:0]
OSDIN2
OSDIN1
OSDIN0
DAC3_OUT
DAC2_OUT
AVSS_DAC
AVDD_DAC
DAC1_OUT
DAC0_OUT
COMP
I/O
O
I
I
O
I
I
I
O
O
G
P
O
O
O
46
VREFDAC
I/O
47
RSET
I
48
49–52, 55, 56,
59–62
53
54
57, 58
63
RESET
DAC_DATA[9:0]
I
I
DVSS
DVDD
DAC_CLK[1:0]
SYNC_OUT
G
P
I
O
Ground for Digital Core Supply
Analog Supply Voltage for Digital Core (5 V or 3.3 V)
DAC Clocks
Output Sync Signal, which goes to a high state while Cr data sample from a
YCrCb data stream or C data from a Y/C data stream is output on DOUT[9:0].
If the SPI interface is enabled, this pin is serial data In. If the I
2
C interface is
enabled, this pin is MPU Port Serial Data Input/Output.
64
SI_SDA
I/O
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