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參數(shù)資料
| 型號(hào)： | ADV7202 |
| 廠商： | Analog Devices, Inc. |
| 元件分類(lèi)： | Codec |
| 英文描述： | Simultaneous Sampling Video Rate Codec |
| 中文描述： | 同時(shí)采樣率視頻編解碼器 |
| 文件頁(yè)數(shù)： | 22/26頁(yè) |
| 文件大小： | 216K |
| 代理商： | ADV7202 |
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REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–22–
TIMING REGISTER
TR (TR00–TR07)
(Address (SR4–SR0) = 0AH)
Figure 29 shows the various operations under the control of the
Timing Register.
TR BIT DESCRIPTION
Crystal Oscillator Circuit (TR00)
If this bit is set to “0,” the internal oscillator circuit will be
disabled. Disabling the oscillator circuit is possible when an
external clock module is used, thus, saving power.
ADC Bias Currents (TR01)
If this bit is set to “1,” all analog bias currents will be doubled.
Duty Cycle Equalizer (TR03)
When this bit is set to “1,” the clock duty cycle equalizer circuit
is active. This will only have an effect on the ADC operation.
The digital core clock will not be affected.
Clock Delay (TR05–TR06)
Using these two bits, it is possible to insert a delay in the clock
signal to the digital core. These bits control the insertion of
the delay.
Reserved (TR02, TR04, TR07)
Zero must be written to the bits in these registers.
TR01
TR07
TR02
TR04
TR05
TR06
ZERO MUST BE
WRITTEN TO
THIS BIT
TR07
TR03
TR00
TR00
0
1
DISABLE
ENABLE
CRYSTAL
OSC. CKT
TR06
0
0
1
1
TR05
0
1
0
1
0ns
4ns
6ns
8ns
CLOCK DELAY
TR01
0
1
INACTIVE
ACTIVE
DUTY CYCLE
EQUALIZER
TR01
0
1
NORMAL
DOUBLE
ADC BIAS
CURRENTS
ZERO MUST BE
WRITTEN TO
THIS BIT
ZERO MUST BE
WRITTEN TO
THIS BIT
TR04
TR02
Figure 29. Timing Register 0
VREF ADJUST REGISTER
VR (VR00–VR07)
(Address (SR4–SR0) = 0AH)
Figure 30 shows the various operations under the control of the
VREF Adjust Register.
VR BIT DESCRIPTION
Reserved (VR00)
This register is reserved and “1” must be written to this bit.
Reserved (VR01–VR03)
Zero must be written to these registers.
Reference Voltage Adjust (VR04–VR06)
By setting the value of this 3-bit word, it is possible to trim the
ADC internal voltage reference VREFADC.
Reserved (VR07)
Zero must be written to this register.
VR01
VR07
VR02
VR04
VR05
VR06
ZERO MUST BE
WRITTEN TO
THIS BIT
VR07
VR03
VR00
VR06 VR05
0
0
0
0
1
1
1
1
VR04
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
DEFAULT NOMINAL
+14mV
+28mV
+42mV
–
14mV
–
28mV
–
42mV
–
56mV
ADC REFERENCE VOLTAGE ADJUST
ZERO MUST BE
WRITTEN TO
THESE BITS
VR03
–
VR01
ONE MUST BE
WRITTEN TO
THIS BIT
VR00
Figure 30. ADC VREF Register
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| ADV7280ABCPZ-M | 功能描述:10-BIT SD VIDEO DECODER 制造商:analog devices inc. 系列:- 包裝:托盤(pán) 零件狀態(tài):在售 類(lèi)型:視頻 數(shù)據(jù)接口:I2C，串行 分辨率（位）:10 b ADC/DAC 數(shù):1 / 0 三角積分:無(wú) 信噪比，ADC/DAC（db）（典型值）:- 動(dòng)態(tài)范圍，ADC/DAC（db）（典型值）:- 電壓 - 電源，模擬:1.71 V ~ 1.89 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-WFQFN 裸露焊盤(pán)，CSP 供應(yīng)商器件封裝:32-LFCSP-WQ（5x5） 標(biāo)準(zhǔn)包裝:1 |
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