參數(shù)資料
型號: ADV7202
廠商: Analog Devices, Inc.
元件分類: Codec
英文描述: Simultaneous Sampling Video Rate Codec
中文描述: 同時采樣率視頻編解碼器
文件頁數(shù): 17/26頁
文件大?。?/td> 216K
代理商: ADV7202
REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–17–
MODE REGISTER 0
MR0 (MR07–MR00)
(Address (SR4–SR0) = 00H)
Figure 20 shows the various operations under the control of
Mode Register 0.
MR0 BIT DESCRIPTION
ADC Reference Voltage (MR00)
This control bit is used to select the ADC reference voltage.
When this bit is set to “0,” a reference voltage of 1.1 V is
selected. When the bit is set to “1,” a reference voltage of 2.2 V
is selected.
External Reference Enable (MR01)
Setting this bit to “1” enables an external voltage reference for
the ADC.
Voltage Reference Power-Down (MR02)
Setting this bit to “1” causes the internal ADC voltage reference to
power down.
ADC Power-Down (MR03)
Setting this bit to “1” causes the video rate ADC to power down.
Power-Down (MR04)
Setting this bit to “1” puts the device into power-save mode.
Reserved (MR05–07)
“0” must be written to these bits.
MR1
MR7
MR2
MR4
MR6
MR3
MR0
MR14
0
1
NORMAL
POWER-DOWN
POWER-DOWN
MR2
0
1
NORMAL
POWER-DOWN
V
POWER-DOWN
MR0
0
1
1.1V
2.2V
ADC REF
VOLTAGE
MR3
0
1
NORMAL
POWER-DOWN
ADC
POWER-DOWN
MR1
0
1
INTERNAL
EXTERNAL
EXT REF
ENABLE
MR5
ZERO MUST BE
WRITTEN TO
THESE BITS
MR7
MR5
Figure 20. Mode Register 0
MODE REGISTER 1
MR1 (MR17–MR10)
(Address (SR4–SR0) = 01H)
Figure 21 shows the various operations under the control of
Mode Register 1.
MR1 BIT DESCRIPTION
DAC0 Control (MR10)
Setting this bit to “0” enables DAC 0; otherwise, this DAC is
powered down.
DAC1 Control (MR11)
Setting this bit to “0” enables DAC 1; otherwise, this DAC is
powered down.
DAC2 Control (MR12)
Setting this bit to “0” enables DAC 2; otherwise, this DAC is
powered down.
DAC3 Control (MR13)
Setting this bit to “0” enables DAC 3; otherwise, this DAC is
powered down.
Dual Edge Clock (MR14)
Setting this bit to “1” allows data to be read into the DACs on
both edges of the clock; hence, data may be read in at twice the
clock frequency. See Figure 21. If this bit is set to “0,” the data
will only be strobed on the rising edge of the clock.
Dual Clock (MR15)
Setting this bit to “1” allows the use of two clocks to strobe data
into the DACs. It is possible to clock data in with only one clock
and use the second clock to contain timing information.
4:2:2 Mode (MR16)
Setting this bit to “1” enables data to be input in 4:2:2 format
(see Figure 21). 4:2:2 mode will only work if TR14 and TR15
register bits are set to zero.
DAC Input Invert (MR17)
Setting this bit to “1” causes the input data to the DACs to be
inverted allowing for an external inverting amplifier.
MR17
MR12
MR14
MR16
MR14
0
1
SINGLE EDGE
DUAL EDGE
DUAL EDGE CLOCK
MR15
MR16
0
1
DISABLE
ENABLE
4:2:2 MODE
MR15
0
1
SINGLE CLK
DUAL CLK
DUAL CLOCK
MR13
MR11
MR10
MR13
0
1
NORMAL
POWER-DOWN
DAC3 CONTROL
MR17
0
1
DISABLE
ENABLE
DAC I/P INVERT
MR12
0
1
NORMAL
POWER-DOWN
DAC2 CONTROL
MR10
0
1
NORMAL
POWER-DOWN
DAC0 CONTROL
MR11
0
1
NORMAL
POWER-DOWN
DAC1 CONTROL
Figure 21. Mode Register 1
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