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| 型號(hào)： | ADV7202 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Simultaneous Sampling Video Rate Codec |
| 中文描述： | 同時(shí)采樣率視頻編解碼器 |
| 文件頁數(shù)： | 10/26頁 |
| 文件大?。?/td> | 216K |
| 代理商： | ADV7202 |
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REV. PrB
PRELIMINARY TECHNICAL DATA
ADV7202
–10–
FUNCTIONAL DESCRIPTION
Analog Inputs
The ADV7202 has the capability of sampling up to five CVBS
video input signals, or two component YUV, or three S-Video
inputs. Eight auxiliary general-purpose inputs are also available.
Table I shows the analog signal input options available and pro-
grammable by I
2
C/SPI. When configured for auxiliary input
mode, the CVBS inputs are single-ended with the second differ-
ential input internally set to VREFADC. The resolution on the
front end digitizer is 12 bits; two bits (12 dB) are used for gain
and offset adjustment. The digitizer has a conversion rate of up
to 54 MHz. The eight auxiliary inputs can be used for system
monitoring, etc., and are sampled by a 843 kHz SAR ADC. The
analog input signal range will be dependent on the value of
VREFADC and the SHA gain see (Table II). Three on-screen
display inputs OSDIN[2:0] mux to the DAC outputs to enable
support for Picture-on-Picture applications.
Table I. Analog Input Signal Data
Register
Setting
SHA
Used
Description
Sync_Out
0000
0001
0010
0011
0100
0101
0110
0111
1000
CVBS in on AIN1
CVBS in on AIN2
CVBS in on AIN3
Reserved
CVBS in on AIN5
CVBS in on AIN6
Y/C, Y on AIN1, C on AIN4
Y/C, Y on AIN2, C on AIN3
YUV, Y on AIN2, U on AIN3, 0, 1, 2 Figure 3
V on AIN6
CVBS on AIN1 and 8 AUX.
I/Ps AIN3–6
*
CVBS on AIN2 and 8 AUX.
I/Ps AIN3–6
*
0
0
1
1
0
2
0, 1
0, 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 1
Figure 2
Figure 2
1001
0, 1, 2 Figure 1
1010
0, 1, 2 Figure 1
*
AUX inputs are single-ended. All other inputs are differential.
Table II. Analog Input Signal Range
I/P
Mode
SHA
Input Range (V)
Min
V
REFOUT
(V) Gain
2.2
2.2
1.1
1.1
Typ
Max
Differential
Differential
Differential
Differential
Single-ended 2.2
Single-ended 2.2
Single-ended 1.1
Single-ended 1.1
1
2
1
2
1
2
1
2
–2.2
–1.1
–1.1
–0.55
0
1.1
0
0.55
0
0
0
0
2.2
2.2
1.1
1.1
2.2
1.1
1.1
0.55
4.4
3.3
2.2
1.65
Digital Inputs
The DAC digital inputs on the ADV7202 [9:0] are TTL-com-
patible. Data may be latched into the device in three different
modes programmable via I
2
C or SPI.
DAC Mode 1, single clock, single edge (see Figure 13) uses only
the rising edge of DAC_CLK1 to latch data into the device.
DAC_CLK0 is a data line that goes high to indicate that the data
is for DAC0. Subsequent data words go to the next DAC in
sequence.
DAC Mode 2, dual edge, dual clock (see Figure 14) clocks data
in on both edges of DAC_CLK0 and DAC_CLK1. Using this
option, data can is latched into the device at four times the
clock speed.
DAC Mode 3, 4:2:2 mode (see Figure 15). Using this option, 4:2:2
video data is latched in using DAC_CLK1, while DAC_CLK0 is used
as a data line that is brought to a high state when Cr data is input;
hence Y will appear on DAC1, Cr on DAC2, and Cb on DAC0.
Analog Outputs
Analog Outputs [DAC0–3] consist of four 10-bit DACs that run at
up to 54 MHz or up to 108 MHz if only DAC0 is used. These outputs
can be used to output CVBS, S-Video, Component YCrCb, and RGB.
Digital Outputs
Video data will be clocked out on DOUT[9:0] during the rising
edge of XTAL0. See Figure 17. Auxiliary data can be read out
vial
2
C compatible MPU port.
I
2
C and SPI Control
The ADV7202 is both I
2
C- and SPI-compatible. It should be
noted though that only register write applications are possible
with SPI control. I
2
C operation allows both reading and writing
of system registers. Its operation is explained in detail in the MPU
Port Description section. A logic high level on the SPI_SEL line
selects SPI MPU operation. In this mode the first eight bits of
the 16-bit word on the SI data line will select the register address
and the next eight bits are the value to be programmed into the
register, i.e., the register data. See Figure 10. Latch Enable (LE)
goes low while valid address or data information is present. Figure
10 shows latch enable low for the entire 16 bits of address and
data information. As shown in Figure 11, the register eight-bit data
information does not always have to be clocked in directly after
the address. LE may go high and then low again when valid data
is available. If LE goes low for anything less than eight cycles of
SCLK, the SPI MPU will reset (not register values); hence this
method may be used to initiate a start condition.
NOTE
Fclk/32, 843kHz for nominal 27 Mhz
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