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參數(shù)資料
| 型號： | ADUC843BSZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 39/88頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 52-MQFP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 44 of 88
Mode 4: Dual NRZ 16-Bit ∑- DAC
Mode 4 provides a high speed PWM output similar to that of a
∑
- DAC. Typically, this mode is used with the PWM clock
equal to 16.777216 MHz. In this mode, P2.6 and P2.7 are
updated every PWM clock (60 ns in the case of 16 MHz). Over
any 65536 cycles (16-bit PWM) PWM0 (P2.6) is high for
PWM0H/L cycles and low for (65536 – PWM0H/L) cycles.
Similarly, PWM1 (P2.7) is high for PWM1H/L cycles and low
for (65536 – PWM1H/L) cycles.
For example, if PWM1H is set to 4010H (slightly above one
quarter of FS), then typically P2.7 will be low for three clocks
and high for one clock (each clock is approximately 60 ns). Over
every 65536 clocks, the PWM compensates for the fact that the
output should be slightly above one quarter of full scale by
having a high cycle followed by only two low cycles.
16.777MHz
16-BIT
60
s
0
16-BIT
CARRY OUT AT P1.0
CARRY OUT AT P2.7
PWM0H/L = C000H
PWM1H/L = 4000H
00
1
00
0
LATCH
0
11
1
0
03260-0-050
60
s
Figure 51. PWM Mode 4
For faster DAC outputs (at lower resolution), write 0s to the
LSBs that are not required. If, for example, only 12-bit perform-
ance is required, write 0s to the four LSBs. This means that a 12-bit
accurate ∑- DAC output can occur at 4.096 kHz. Similarly
writing 0s to the 8 LSBs gives an 8-bit accurate ∑- DAC output
at 65 kHz.
Mode 5: Dual 8-Bit PWM
In Mode 5, the duty cycle of the PWM outputs and the resolu-
tion of the PWM outputs are individually programmable. The
maximum resolution of the PWM output is 8 bits. The output
resolution is set by the PWM1L and PWM1H SFRs for the P2.6
and P2.7 outputs, respectively. PWM0L and PWM0H sets the
duty cycles of the PWM outputs at P2.6 and P2.7, respectively.
Both PWMs have the same clock source and clock divider.
P2.7
P2.6
PWM COUNTERS
PWM1H
0
PWM1L
PWM0H
PWM0L
03260-0-051
Figure 52. PWM Mode 5
Mode 6: Dual RZ 16-Bit ∑- DAC
Mode 6 provides a high speed PWM output similar to that of a
∑
- DAC. Mode 6 operates very similarly to Mode 4. However,
the key difference is that Mode 6 provides return-to-zero (RZ)
∑
- DAC output. Mode 4 provides non-return-to-zero ∑-
DAC outputs. The RZ mode ensures that any difference in the
rise and fall times will not affect the ∑- DAC INL. However,
the RZ mode halves the dynamic range of the ∑- DAC outputs
from 0 V–AVDD down to 0 V–AVDD/2. For best results, this mode
should be used with a PWM clock divider of 4.
If PWM1H is set to 4010H (slightly above one quarter of FS),
typically P2.7 will be low for three full clocks (3 × 60 ns), high
for half a clock (30 ns), and then low again for half a clock
(30 ns) before repeating itself. Over every 65536 clocks, the
PWM will compensate for the fact that the output should be
slightly above one quarter of full scale by leaving the output
high for two half clocks in four. The rate at which this happens
depends on the value and degree of compensation required.
4MHz
16-BIT
240
s
0
16-BIT
CARRY OUT AT P2.6
CARRY OUT AT P2.7
PWM0H/L = C000H
PWM1H/L = 4000H
00 1
00
0
LATCH
0 11
1
0
240
s
0, 3/4, 1/2, 1/4, 0
03260-0-052
Figure 53. PWM Mode 6
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