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參數(shù)資料
| 型號： | ADUC843BSZ62-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 52-MQFP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | DMA，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 32 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
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ADuC841/ADuC842/ADuC843
Rev. 0 | Page 39 of 88
Using the DAC
The on-chip DAC architecture consists of a resistor string DAC
followed by an output buffer amplifier, the functional equivalent
of which is illustrated in Figure 42. Details of the actual DAC
architecture can be found in U.S. Patent Number 5969657
(www.uspto.gov). Features of this architecture include inherent
guaranteed monotonicity and excellent differential linearity.
OUTPUT
BUFFER
HIGH Z
DISABLE
(FROM MCU)
DAC0
R
ADuC841/ADuC842
AVDD
VREF
03260-0-041
Figure 42. Resistor String DAC Functional Equivalent
As shown in Figure 42, the reference source for each DAC is
user selectable in software. It can be either AVDD or VREF. In
0 V-to-AVDD mode, the DAC output transfer function spans
from 0 V to the voltage at the AVDD pin. In 0 V-to-VREF mode,
the DAC output transfer function spans from 0 V to the internal
VREF or, if an external reference is applied, the voltage at the CREF
pin. The DAC output buffer amplifier features a true rail-to-rail
output stage implementation. This means that unloaded, each
output is capable of swinging to within less than 100 mV of
both AVDD and ground. Moreover, the DAC’s linearity specifica-
tion (when driving a 10 k resistive load to ground) is guaranteed
through the full transfer function except Codes 0 to 100, and, in
0 V-to-AVDD mode only, Codes 3995 to 4095. Linearity degrada-
tion near ground and VDD is caused by saturation of the output
amplifier, and a general representation of its effects (neglecting
offset and gain error) is illustrated in Figure 43. The dotted line
in Figure 43 indicates the ideal transfer function, and the solid
line represents what the transfer function might look like with
endpoint nonlinearities due to saturation of the output amplifier.
Note that Figure 43 represents a transfer function in 0 V-to-VDD
mode only. In 0 V-to-VREF mode (with VREF < VDD), the lower
nonlinearity would be similar, but the upper portion of the
transfer function would follow the ideal line right to the end
(VREF in this case, not VDD), showing no signs of endpoint
linearity errors.
VDD
VDD–50mV
VDD–100mV
100mV
50mV
0mV
000H
FFFH
03260-
0-
042
Figure 43. Endpoint Nonlinearities Due to Amplifier Saturation
SOURCE/SINK CURRENT (mA)
5
0
5
10
15
OUTPUT
VOLTAGE
(V)
4
3
2
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
03260-0-043
Figure 44. Source and Sink Current Capability with VREF = VDD = 5 V
SOURCE/SINK CURRENT (mA)
4
0
5
10
15
OUTPUT
VOLTAGE
(V)
3
1
0
DAC LOADED WITH 0000H
DAC LOADED WITH 0FFFH
03260-0-044
Figure 45. Source and Sink Current Capability with VREF = VDD = 3 V
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