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參數(shù)資料
| 型號： | ADUC836BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/80頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 62K FLASH ADC/DAC 56LFCSP |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 62KB（62K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉換器： | A/D 7x16b; D/A 1x12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 包裝： | 托盤 |
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ADuC836
–38–
ADuC836
–39–
ON-CHIP PLL
The ADuC836 is intended for use with a 32.768 kHz watch
crystal. A PLL locks onto a multiple (384) of this to provide a
stable 12.582912 MHz clock for the system. The core can
operate at this frequency, or at binary submultiples of it, to allow
power saving in cases where maximum core performance is not
required.The default core clock is the PLL clock divided by
8 or 1.572864 MHz.The ADC clocks are also derived from the
PLL clock, with the modulator rate being the same as the crystal
oscillator frequency.This choice of frequencies ensures that the
modulators and the core will be synchronous, regardless of the
core clock rate.The PLL control register is PLLCON.
Table XVII. PLLCON SFR Bit Designations
Bit
Name
Description
7
OSC_PD
Oscillator Power-Down Bit.
Set by user to halt the 32 kHz oscillator in Power-Down mode.
Cleared by user to enable the 32 kHz oscillator in Power-Down mode.
This feature allows the TIC to continue counting even in Power-Down mode.
6
LOCK
PLL Lock Bit.This is a read-only bit.
Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. After
power-down, this bit can be polled to wait for the PLL to lock.
Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock.This may
be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output
can be 12.58 MHz ± 20%. After the ADuC836 wakes up from power-down, user code may poll this bit
to wait for the PLL to lock. If LOCK = 0, then the PLL is not locked.
5
–––
Reserved for Future Use. Should be written with 0.
4
LTEA
Reading this bit returns the state of the external EA pin latched at reset or power-on.
3
FINT
Fast Interrupt Response Bit.
Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency,
regardless of the configuration of the CD2–0 bits (see below). After user code has returned from an interrupt,
the core resumes code execution at the core clock selected by the CD2–0 bits. Cleared by user to disable
the fast interrupt response feature.
2
CD2
CPU (Core Clock) Divider Bits.
1
CD1
This number determines the frequency at which the microcontroller core will operate.
0
CD0
CD2
CD1
CD0
Core Clock Frequency (MHz)
0
12.582912
0
1
6.291456
0
1
0
3.145728
0
1
1.572864 (Default Core Clock Frequency)
1
0
0.786432
1
0
1
0.393216
1
0
0.196608
1
0.098304
PLLCON
PLL Control Register
SFR Address
D7H
Power-On Default Value
03H
Bit Addressable
No
REV. A
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| ADUC836BCPZ-REEL | 功能描述:IC MCU 62K FLASH ADC/DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MicroConverter® ADuC8xx 標準包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設備:欠壓檢測/復位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲器容量:4KB（4K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉換器:- 振蕩器型:內部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
| ADUC836BS | 制造商:Analog Devices 功能描述:MCU 8-bit ADuC8xx 8052 CISC 62KB Flash 3.3V/5V 52-Pin MQFP 制造商:Analog Devices 功能描述:8BIT MCU +16BIT DUAL ADC MQFP52 |
| ADUC836BS | 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
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| ADUC841 | 制造商:AD 制造商全稱:Analog Devices 功能描述:MicroConverter 12-Bit ADCs and DACs with Embedded High Speed 62-kB Flash MCU |
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