參數(shù)資料
型號(hào)： ADUC836BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/80頁(yè)
文件大?。?/td> 0K
描述： IC MCU 62K FLASH ADC/DAC 56LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，PWM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 62KB（62K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量： 2.25K x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 7x16b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 56-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC836
–20–
ADuC836
–21–
ADC0H/ADC0M (Primary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the primary ADC.
SFR Address
ADC0H
High Data Byte
DBH
ADC0M
Middle Data Byte
DAH
Power-On Default Value
00H
ADC0H, ADC0M
Bit Addressable
No
ADC0H, ADC0M
ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers)
These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC.
SFR Address
ADC1H
High Data Byte
DDH
ADC1L
Low Data Byte
DCH
Power-On Default Value
00H
ADC1H, ADC1L
Bit Addressable
No
ADC1H, ADC1L
OF0H/OF0M (Primary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the primary ADC.These registers are configured at power-on
with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale
calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register.
SFR Address
OF0H
Primary ADC Offset Coefficient High Byte
E3H
OF0M
Primary ADC Offset Coefficient Middle Byte
E2H
Power-On Default Value
80000H
OF0H, OF0M respectively
Bit Addressable
No
OF0H, OF0M
OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*)
These two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary ADC.These registers are configured at power-on
with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration
of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register.
SFR Address
OF1H
Auxiliary ADC Offset Coefficient High Byte
E5H
OF1L
Auxiliary ADC Offset Coefficient Low Byte
E4H
Power-On Default Value
8000H
OF1H and OF1L, respectively
Bit Addressable
No
OF1H, OF1L
GN0H/GN0M (Primary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the primary ADC.These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes
will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via MD2–0
bits in the ADCMODE Register.
SFR Address
GN0H
Primary ADC Gain Coefficient High Byte
EBH
GN0M
Primary ADC Gain Coefficient Middle Byte
EAH
Power-On Default Value
Configured at Factory Final Test; See Notes above.
Bit Addressable
No
GN0H, GN0M
GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*)
These two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary ADC.These registers are configured at power-on
with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes
will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0
bits in the ADCMODE Register.
SFR Address
GN1H
Auxiliary ADC Gain Coefficient High Byte
EDH
GN1L
Auxiliary ADC Gain Coefficient Low Byte
ECH
Power-On Default Value
Configured at Factory Final Test; see notes above.
Bit Addressable
No
GN1H, GN1L
*These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero.
REV. A
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