CPHA1 Clock Phase Select Bit. Set by the user" />
參數(shù)資料
型號(hào)： ADUC814BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 40/72頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT W/FLASH MCU 28TSSOP
標(biāo)準(zhǔn)包裝： 50
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 17
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 738 (CN2011-ZH PDF)
配用： EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 45 of 72
Bit No.
Name
Description
2
CPHA1
Clock Phase Select Bit.
Set by the user if the leading SCLOCK edge is to transmit data.
Cleared by the user if the trailing SCLOCK edge is to transmit data.
1
SPR1
SPI Bit Rate Select Bits.
0
SPR0
These bits select the SCLOCK rate (bit rate) in master mode as follows:
SPR1
SPR0
Selected Bit Rate
0
fCORE/2
0
1
fCORE/4
1
0
fCORE/8
1
fcore/16
In SPI slave mode,where SPIM = 0, the logic level on the external SS pin (Pin 22), can be read via the SPR0 bit.
1The CPOL and CPHA bits should both contain the same values for master and slave devices.
SPIDAT
SPI Data Register
Function
The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by the user code to read
data just received by the SPI interface.
SFR Address
F7H
Power-On Default
00H
Bit Addressable
No
Using the SPI Interface
Depending on the configuration of the bits in the SPICON SFR
shown in Table 18, the ADuC814 SPI interface transmits or
receives data in a number of possible modes. Figure 44 shows all
possible ADuC814 SPI configurations and the timing relation-
ships and synchronization between the signals involved.
SCLOCK
(CP0L = 0)
SCLOCK
(CP0L = 1)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
?
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
02748-
A
-050
Figure 44. ADuC814, SPI Timing, All Modes
SPI Interface—Master Mode
In master mode, the SCLOCK pin is always an output and
generates a burst of eight clocks whenever user code writes to
the SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the SS
pin is not used in master mode. If the ADuC814 needs to assert
the SS pin on an external slave device, a port digital output pin
should be used. In master mode, a byte transmission or reception
is initiated by a write to SPIDAT. Eight clock periods are gener-
ated via the SCLOCK pin and the SPIDAT byte being transmitted
via MOSI. With each SCLOCK period, a data bit is also sampled
via MISO. After eight clocks, the byte is completely transmitted,
and the input byte is waiting in the input shift register. The ISPI
flag is set automatically and an interrupt occurs if enabled. The
value in the shift register is latched into SPIDAT.
SPI Interface—Slave Mode
In slave mode, the SCLOCK is an input. The SS pin must also be
driven low externally during the byte communication. Trans-
mission is also initiated by a write to SPIDAT. In slave mode, a
data bit is transmitted via MISO, and a data bit is received via
MOSI on each input SCLOCK. After eight clocks, the byte is
completely transmitted and the input byte is waiting in the
input shift register. The ISPI flag is set automatically and an
interrupt occurs if enabled. The value in the shift register is
latched into SPIDAT only when the transmission/reception of a
byte is complete. The end of transmission occurs after the
eighth clock is received, if CPHA = 1, or when SS returns high if
CPHA = 0.
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