參數(shù)資料
型號: ADUC814BRUZ
廠商: Analog Devices Inc
文件頁數(shù): 16/72頁
文件大?。?/td> 0K
描述: IC ADC 12BIT W/FLASH MCU 28TSSOP
標(biāo)準(zhǔn)包裝: 50
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 16.78MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 17
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 6x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 738 (CN2011-ZH PDF)
配用: EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 23 of 72
ADCCON2 (ADC CONTROL SFR 2)
The ADCCON2 (byte addressable) register controls ADC channel selection and conversion modes as detailed below.
SFR Address
D8H
SFR Power-On Default
00H
Bit Addressable
Yes
ADCI
ADCSPI
CCONV
SCOVC
CS3
CS2
CS1
CS0
Table 7. ADCCON2 SFR Bit Designations
Bit No.
Name
Description
7
ADCI
ADC Interrupt Bit.
ADCI is set at the end of a single ADC conversion cycle. If the ADC interrupt is enabled, the ADCI bit is cleared when
user code vectors to the ADC interrupt routine. Otherwise the ADCI bit should be cleared by the user code.
6
ADCSPI
ADCSPI Mode Enable Bit.
ADCSPI is set to enable the ADC conversion results to be transferred directly to the SPI data buffer (SPIDAT) without
intervention from the CPU.
5
CCONV
Continuous Conversion Bit.
CCONV is set to initiate the ADC into a continuous mode of conversion. In this mode the ADC starts converting
based on the timing and channel configuration already set up in the ADCCON SFRs. The ADC automatically starts
another conversion once a previous conversion cycle has completed. When operating in this mode from 3 V
supplies, the ADC should be configured for ADC clock divide of 16 using CK1 and CK0 bits in ADCCON1, and ADC
acquisition time should be set to four ADC clocks using AQ1, AQ0 bits in ADCCON1 SFR.
4
SCONV
Single Conversion Bit.
SCONV is set to initiate a single conversion cycle. The SCONV bit is automatically reset to 0 on completion of the
single conversion cycle. When operating in this mode from 3 V supplies, the maximum ADC sampling rate should
not exceed 147 kSPS.
3
CS3
Channel Selection Bits.
2
1
CS2
CS1
CS3–CS0 allow the user to program the ADC channel selection under software control. Once a conversion is
initiated, the channel converted is pointed to by these channel selection bits.
0
CS0
The Channel Select bits operate as follows:
CS3
CS2
CS1
CS0
CHANNEL
0
1
0
1
0
2
0
1
3
0
1
0
4
0
1
0
1
5
0
1
0
X
Not a vaild selection. No ADC channel selected.
0
1
X
Not a valid selection. No ADC channel selected.
1
0
Temperature Sensor
1
0
1
DAC0
1
0
1
0
DAC1
1
0
1
AGND
1
0
VREF
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