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參數(shù)資料
| 型號(hào)： | ADUC814BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 25 of 72
DRIVING THE ADC
The ADC incorporates a successive approximation architecture
(SAR) involving a charge-sampled input stage. Each ADC con-
version is divided into two distinct phases as defined by the
position of the switches in Figure 25. During the sampling
phase (with SW1 and SW2 in the track position), a charge
proportional to the voltage on the analog input is developed
across the input sampling capacitor. During the conversion
phase (with both switches in the hold position), the capacitor
DAC is adjusted via internal SAR logic until the voltage on
Node A is zero, indicating that the sampled charge on the input
capacitor is balanced out by the charge being output by the
capacitor DAC. The digital value finally contained in the SAR is
then latched out as the result of the ADC conversion. Control of
the SAR, and timing of acquisition and sampling modes, is han-
dled automatically by built-in ADC control logic. Acquisition and
conversion times are also fully configurable under user control.
COMPARATOR
VREF
AGND
DAC1
DAC0
TEMPERATURE MONITOR
INTERNAL
CHANNELS
AIN5
AIN0
32pF
AGND
ADuC814
TRACK
HOLD
200
200
02748-A
-032
CAPACITOR
DAC
Figure 25. Internal ADC Structure
Note that whenever a new input channel is selected, a residual
charge from the 32 pF sampling capacitor places a transient on
the newly selected input. The signal source must be capable of
recovering from this transient before the sampling switches
click into hold mode. Delays can be inserted in software
(between channel selection and conversion request) to account
for input stage settling, but a hardware solution alleviates this
burden from the software design task and ultimately results in a
cleaner system implementation.
One hardware solution is to choose a very fast settling op amp
to drive each analog input. Such an op amp would need to fully
settle from a small signal transient in less than 300 ns in order
to guarantee adequate settling under all software configurations.
A better solution, recommended for use with any amplifier, is
shown in Figure 26.
AIN0
ADuC814
10
0.1
F
02748-A
-033
Figure 26. Buffering Analog Inputs
At first glance the circuit in Figure 26 may look like a simple
anti-aliasing filter, it actually serves no such purpose. Though
the R/C does help to reject some incoming high frequency noise,
its primary function is to ensure that the transient demands of
the ADC input stage are met. It does so by providing a capacitive
bank from which the 32 pF sampling capacitor can draw its
charge. Since the 0.1 F capacitor in Figure 26 is more than
3000 times the size of the 32 pF sampling capacitor, its voltage
does not change by more than one count of the 12-bit transfer
function when the 32 pF charge from a previous channel is
dumped onto it. A larger capacitor can be used if desired, but
care needs to be taken if choosing a larger resistor (see Table 9).
The Schottky diodes in Figure 26 may be necessary to limit the
voltage applied to the analog input pin as per the Absolute
Maximum Ratings. They are not necessary if the op amp is
powered from the same supply as the ADuC814 because, in that
case, the op amp is unable to generate voltages above VDD or
below ground. An op amp of some kind is necessary unless the
signal source is very low impedance to begin with. DC leakage
currents at the ADuC814 analog inputs can cause measurable
dc errors with external source impedances as little as 100 or
so. To ensure accurate ADC operation, keep the total source
impedance at each analog input less than 61 . Table 9 illustrates
examples of how source impedance can affect dc accuracy.
Table 9. Source Impedance Errors
Source
Impedance
Error from 1 A
Leakage Current
Error from 10 A
Leakage Current
61
61 V = 0.1 LSB
610 V = 1 LSB
610
610 V = 1 LSB
6.1 mV = 10 LSB
Although Figure 26 shows the op amp operating at a gain of 1,
you can configure it for any gain needed. Also, you can just as
easily use an instrumentation amplifier in its place to condition
differential signals. Use any modern amplifier that is capable of
delivering the signal (0 V to VREF) with minimal saturation.
Some single-supply, rail-to-rail op-amps that are useful for this
purpose include, but are certainly not limited to, the ones given
in Table 10. Check the Analog Devices literature (CD ROM data
book, etc.) for details on these and other op amps and
instrumentation amps.
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