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參數(shù)資料
| 型號： | ADUC814BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 19/72頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT W/FLASH MCU 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 16.78MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 17 |
| 程序存儲器容量： | 8KB（8K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 6x12b; D/A 2x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 738 (CN2011-ZH PDF) |
| 配用： | EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR |
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ADuC814
Rev. A | Page 26 of 72
Table 10. Some Single-Supply Op Amps
Op Amp Model
Characteristics
OP281/OP481
Micropower
OP191/OP291/OP491
I/O good up to VDD, low cost
OP196/OP296/OP496
I/O to VDD, micropower, low cost
OP183/OP283
High gain-bandwidth product
OP162/OP262/OP462
High GBP, micropackage
AD820/OP822/OP824
FET input, low cost
AD823
FET input, high GBP
Keep in mind that the ADC’s transfer function is 0 V to VREF,
and any signal range lost to amplifier saturation near ground
impacts dynamic range. Though the op amps in Table 10 are
capable of delivering output signals very closely approaching
ground, no amplifier can deliver signals all the way to ground
when powered by a single supply. Therefore, if a negative supply
is available, one could consider using it to power the front end
amplifiers. If you do, however, be sure to include the Schottky
diodes shown in Figure 26 (or at least the lower of the two
diodes) to protect the analog input from undervoltage conditions.
VOLTAGE REFERENCE CONNECTIONS
The on-chip 2.5 V band gap voltage reference can be used as the
reference source for the ADC and DACs. To ensure the accuracy
of the voltage reference, decouple the VREF and the CREF pin to
ground with 0.1 F capacitors as shown in Figure 27.
BUFFER
0.1
F
0.1
F
VREF
CREF
2.5V
BAND GAP
REFERENCE
TO ADC
REFERENCE
INPUT
ADuC814
02748-A
-034
Figure 27. Decoupling VREF and CREF
If the internal voltage reference is to be used as a reference for
external circuitry, the CREF output should be used. However, a
buffer must be used in this case to ensure that no current is
drawn from the CREF pin itself. The voltage on the CREF pin is
that of an internal node within the buffer block, and its voltage
is critical to ADC and DAC accuracy. As outlined in the
Reference Input/Output section of the Specifications table, the
internal band gap reference takes typically 80 msecs to power
on and settle to its final value. To ensure accurate ADC operation,
one should wait for the ADC to settle after power-on.
If an external voltage reference is preferred, it should be con-
the ADCCON1 SFR must be set to 1 to switch in the external
reference voltage. To ensure accurate ADC operation, the
voltage applied to VREF must be between 1.0 V and AVDD. In
situations where analog input signals are proportional to the
power supply (such as some strain gage applications) it can be
desirable to connect the VREF pin directly to AVDD.
BUFFER
CREF
1 = EXTERNAL
0 = INTERNAL
ADuC814
ADCCON1.6
VDD
02748-
A
-035
2.5V
BAND GAP
REFERENCE
EXTERNAL
VOLTAGE
REFERENCE
TO ADC
REFERENCE
INPUT
0.1
F
0.1
F
VREF
Figure 28. Using an External Voltage Reference
Operation of the ADC with a reference voltage below 1.0 V,
however, may incur loss of accuracy eventually resulting in
missing codes or non-monotonicity. For that reason, do not use
a reference voltage less than 1.0 V.
CONFIGURING THE ADC
In configuring the ADC a number of parameters need to be set
up. These parameters can be configured using the three SFRs:
ADCCON1, ADCCON2, and ADCCON3, which are detailed in
the following sections.
The ADCCLK determines the speed at which the ADC logic
runs while performing an ADC conversion. All ADC timing
parameters are calculated from the ADCCLK frequency. On the
ADuC814, the ADCCLK is derived from the maximum core
frequency (FCORE), 16.777216 MHz. The ADCCLK frequency is
selected via ADCCON1 Bits 5 and 4, which provide four core
clock divide ratios of 8, 4, 16, and 32, generating ADCCLK
values of 2 MHz, 4 MHz, 1 MHz, and 500 kHz, respectively.
The acquisition time (TACQ) is the number of ADCCLKs that
the ADC input circuitry uses to sample the input signal. In most
cases, an acquisition time of one ADCCLK provides more than
adequate time for the ADuC814 to acquire its signal before
switching the internal track-and-hold amplifier into hold mode.
The only exception is a high source impedance analog input,
but this should be buffered first anyway because high source
impedances can cause significant dc errors (see Table 6).
ADCCON1 Bits 3 and 2 are used to select acquisition times of
1, 2, 3, and 4 ADCCLKs.
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