參數(shù)資料
型號： ADUC7034BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 59/136頁
文件大?。?/td> 0K
描述： IC MCU FLASH 32K ANLG IO 48LFCSP
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC7034
Rev. B | Page 29 of 136
Temporary Protection
Temporary protection can be set and removed by writing
directly into the FEE0HID MMR. This register is volatile and,
therefore, protection is only in place for as long as the part
remains powered on. The protection setting is not reloaded
after a power cycle.
Keyed Permanent Protection
Keyed permanent protection can be set via FEE0PRO to lock
the protection configuration. The software key used at the start
of the required FEE0PRO write sequence is saved one time only
and must be used for any subsequent access of the FEE0HID or
FEE0PRO MMRs. A mass erase sets the software protection key
back to 0xFFFF but also erases the entire user code space.
Permanent Protection
Permanent protection can be set via FEE0PRO, similar to how
keyed permanent protection is set, with the only difference
being that the software key used is 0xDEADDEAD. When the
FEE0PRO write sequence is saved, only a mass erase sets the
software protection key back to 0xFFFFFFFF. This also erases
the entire user code space.
Sequence to Write the Software Protection Key and Set
Permanent Protection
1.
Write in FEE0PRO corresponding to the pages to be
protected.
2.
Write the new (user-defined) 32-bit software protection
key in FEE0ADR (Bits[31:16]) and FEE0DAT (Bits[15:0]).
3.
Write 10 in FEE0MOD (Bits[6:5]) and set FEE0MOD (Bit 3).
4.
Run the protect command (Code 0x0C) in FEE0CON.
To remove or modify the protection, the same sequence can be
used with a modified value of FEE0PRO.
The previous sequence for writing the key and setting perma-
nent protection is illustrated in the following example, this
protects writing Page 4 and Page 5 of the Flash/EE:
Int a = FEE0STA;
// Ensure FEE0STA
is cleared
FEE0PRO = 0xFFFFFFFB;
// Protect Page 4
and Page 5
FEE0ADR = 0x66BB;
// 32-bit key
value (Bits[31:16])
FEE0DAT = 0xAA55;
// 32-bit key
value (Bits[15:0])
FEE0MOD = 0x0048
// Lock security
sequence
FEE0CON = 0x0C;
// Write key
command
while (FEE0STA & 0x04){} // Wait for
command to finish
FLASH/EE MEMORY RELIABILITY
The Flash/EE memory array on the part is fully qualified for
two key Flash/EE memory characteristics: Flash/EE memory
cycling endurance and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. A single
endurance cycle is composed of four independent, sequential
events, defined as
Initial page erase sequence
Read/verify sequence
Byte program sequence
Second read/verify sequence
In reliability qualification, every halfword (16 bits wide) location of
the three pages (top, middle, and bottom) in the Flash/EE memory
is cycled 10,000 times from 0x0000 to 0xFFFF. As indicated in
Table 1, the Flash/EE memory endurance qualification of the
part is carried out in accordance with JEDEC Retention Lifetime
Specification A117. The results allow the specification of a
minimum endurance figure over supply and temperature of
10,000 cycles.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the part is
qualified in accordance with the formal JEDEC Retention
Lifetime Specification A117 at a specific junction temperature
(TJ = 85°C). As part of this qualification procedure, the
Flash/EE memory is cycled to its specified endurance limit,
described previously, before data retention is characterized.
This means that the Flash/EE memory is guaranteed to retain
its data for the fully specified retention lifetime every time the
Flash/EE memory is reprogrammed. In addition, note that the
retention lifetime, based on an activation energy of 0.6 eV, derates
with TJ as shown in Figure 14.
0
150
300
450
600
25
40
55
70
85
100
115
130
145
RE
T
E
NT
IO
N
(
Y
ea
rs
)
JUNCTION TEMPERATURE (°C)
07
11
6-
0
12
Figure 14. Flash/EE Memory Data Retention
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