參數(shù)資料
型號： ADUC7034BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 33/136頁
文件大?。?/td> 0K
描述： IC MCU FLASH 32K ANLG IO 48LFCSP
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 1K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC7034
Rev. B | Page 128 of 136
BSD COMMUNICATION FRAME
To transfer data between a master and slave, or vice versa, the
construction of a BSD frame is required. A BSD frame contains
seven key components: pause/sync, direction (DIR) bit, slave
address, register address, data, parity (P1 and P2) bits, and
acknowledge from the slave.
If the master is transmitting data, all bits except the acknowledge bit
are transmitted by the master.
If the master is requesting data from the slave, the master
transmits the pause/sync, direction bit, slave address, register
address, and P1. The slave then transmits the data bytes, the P2,
and the acknowledge in the following sequence:
1.
Pause: ≥ three synchronization pulses.
2.
DIR: signifies the direction of data transfer.
DIR = 0 if master sends request.
DIR = 1 if slave sends request.
3.
Slave address.
4.
Register address: defines register to be read or written.
5.
Bit 3 is set to write and cleared to read.
6.
Data: 8-bit read only receive register.
7.
P1 and P2.
P1 = 0 if even number of 1s in eight previous bits.
P1 = 1 if odd number of 1s in eight previous bits.
P2 = 0 if even number of 1s in data-word.
P2 = 1 if odd number of 1s in data-word.
8.
Acknowledge.
ACK = 0 if transmission is successful.
The acknowledge is always transmitted by the slave to indicate
whether the information was received or transmitted.
Table 95. BSD Protocol Description
Pause
DIR
Slave
Address
Register
Address
P1
Data
P2
ACK
3 bits
1 bit
3 bits
4 bits
1 bit
8 bits
1 bit
BSD Example Pulse Widths
An example of the different pulse widths is shown in Figure 53.
For each bit, the period for which the bus is held low defines
what type of bit it is. If the bit is a sync bit, the pulse is held low
for one bit. If the bit is 0, the pulse is held low for three bits. If
the bit is 1, the pulse is held low for six bits.
If the master is transmitting data, the signal is held low for the
duration of the signal by the master. An example of a master
transmitting 0 is shown in Figure 54. If the slave is transmitting
data, the master pulls the bus low to begin communication. Next,
the slave must pull the bus low before tSYNC elapses and then hold
the bus low until either t0 or t1 has elapsed, after which time the
bus is released by the slave. An example of a slave transmitting a
0 is shown in Figure 55.
tSYNC
t0
t1
07
11
6-
04
9
Figure 53. BSD Bit Transmission
BUS PULLED LOW
BY MASTER
tSYNC
BUS RELEASED BY
MASTER AFTER
t0
07
11
6-
05
0
Figure 54. BSD Master Transmitting 0
BUS PULLED LOW
BY MASTER
BUS RELEASED BY
SLAVE AFTER
t0
BUS HELD LOW
BY SLAVE
RELEASED BY
MASTER
tSYNC
t0
07
11
6-
05
1
Figure 55. BSD Slave Transmitting 0
Typical BSD Program Flow
Because BSD is a PWM communication protocol controlled by
software, the user must construct the required data from each bit.
For example, in constructing the slave address, the slave node
receives the three bits and the user constructs the relevant address.
When BSD communication is initiated by the master, data is
transmitted and received by the slave node. A flow diagram
detailing this process is shown in Figure 56.
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