參數(shù)資料
型號: ADUC7034BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 58/136頁
文件大?。?/td> 0K
描述: IC MCU FLASH 32K ANLG IO 48LFCSP
標準包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設(shè)備: POR,PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 115°C
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
包裝: 托盤
ADuC7034
Rev. B | Page 28 of 136
FEE0DAT Register
Name:
FEE0DAT
Address:
0xFFFF0E0C
Default Value:
0x0000
Access:
Read/write access
Function:
This 16-bit register contains the data either
read from or to be written to the Flash/EE
memory.
FLASH/EE MEMORY SECURITY
The 30 kB of Flash/EE memory available to the user can be read
and write protected using the FFE0HID register.
The FEE0HID MMR protects the 30 kB of Flash/EE memory.
Bits[0:28] of this register write protect Page 0 to Page 57. Each bit
protects two pages, that is, 1 kB. Bit 29 to Bit 30 protect Page 58
and Page 59, respectively; that is, each bit write protects a single
page of 512 bytes. The MSB of this register (Bit 31) protects the
entire Flash/EE from being read through JTAG.
The FEE0PRO register mirrors the bit definitions of the FEE0HID
MMR. The FEE0PRO MMR allows user code to lock the pro-
tection or security configuration of the Flash/EE memory so
that the protection configuration is automatically loaded upon
subsequent power-on or reset events. This flexibility allows
the user to temporarily set and test protection settings using
the FEE0HID MMR and then lock the required protection
configuration (using FEE0PRO) when shipping protection
systems into the field.
There are three levels of protection: temporary protection,
keyed permanent protection, and permanent protection.
Flash/EE Memory Protection Registers
Name:
FEE0HID and FEE0PRO
Address:
0xFFFF0E20 (for FEE0HID) and 0xFFFF0E1C
(for FEE0PRO)
Default Value:
0xFFFFFFFF (for FEE0HID) and 0x00000000
(for FEE0PRO)
Access:
Read/write access
Function:
These registers are written by user code to
configure the protection of the Flash/EE
memory.
Table 16. FEE0HID MMR and FEE0PRO MMR Bit Designations
Bit
Description
31
Read protection bit.
Set by user code to allow read access to the 32 kB Flash/EE block via JTAG.
Cleared by user code to read protect the 32 kB Flash/EE block code.
30
Write protection bit.
Set by user code to allow writes to Page 59.
Cleared by user code to write protect Page 59.
29
Write protection bit.
Set by user code to allow writes to Page 58.
Cleared by user code to write protect Page 58.
28 to 0
Write protection bits.
Set by user code to allow writes to Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two
pages and each page consists of 512 bytes.
Cleared by user code to write protect Page 0 to Page 57 of the 30 kB Flash/EE code memory. Each bit write protects two
pages and each page consists of 512 bytes.
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