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參數(shù)資料
| 型號： | ADUC702X |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 71/80頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC702X |
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Preliminary Technical Data
ADuC702x Series
Rev. PrB | Page 71 of 80
External Memory Interfacing
The only ADuC702x models which feature an external memory
interface are the ADuC7026 and ADuC7027. The external
memory interface requires a larger number of pins, this is why it
is only available on larger pin count package.
The pins required for interfacing to an external memory are:
Pin
Function
AD[15:0}
Address/Data Bus
A16
Extended Addressing
MS[3:0}
Memory Select Pins
WR
Write Strobe
RS
Read Strobe
AE
Address Latch Enable
BHE, BLE
Byte Write Capability
There are four external memory regions available. These are
documented in the table below.
Address Start
Address End
Contents
0x10000000
0x1001FFFF
External Memory 0
0x20000000
0x2001FFFF
External Memory 1
0x30000000
0x3001FFFF
External Memory 2
0x40000000
0x4001FFFF
External Memory 3
Each external memory region can be controlled through the
following three MMRs
XMCFG
is set to 1 to enable external memory access. This
must be set to 1 before any port pins will function as external
memory access pins. The port pins must also be individually
enabled via the
GPxCON
MMR
XMxCON
are registers that enable/disable a memory region.
This register also controls the data bus width of the memory
region.
XMxPAR
are registers that define the protocol used for
accessing the external memory for each memory region.
Table 64: XMxCON MMR Bit Descriptions
Bit
Description
1
Selects between 8 and 16 bit data bus width.
Set by the user to select a 16 bit data bus
Cleared by the user to select an 8 bit data bus.
Enables Memory Region
Set by the user to enable memory region
Cleared by the user to disable the memory region
0
Table 65: XMxPAR MMR Bit Descriptions
Bit
Description
15
Enable Byte write strobe
Set by the user gates the BHE and BLE outputs with the WR output. This allows byte write capability without using
Number of wait states on the Address latch enable strobe.
14-12
11
Enable dynamic addressing
Set by the user to enable 16 bit addressing mode
Cleared by the user to enable 8 bit addressing mode
Extra address hold time
Set by the user to disable extra hold time
Cleared by the user to enable one clock cycle of hold on address in read and write
Extra bus transition time on Read
Set by the user to disable extra bus transition time
10
9
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