參數(shù)資料
型號(hào)： ADUC702X
廠商： Analog Devices, Inc.
元件分類： 32位微控制器
英文描述： Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 52/80頁(yè)
文件大?。?/td> 840K
代理商： ADUC702X
ADuC702x Series
Preliminary Technical Data
SERIAL PORT MUX
Rev. PrB | Page 52 of 80
The Serial Port Mux multiplexes the serial port peripherals (two
I
2
C, SPI, UART) and the Programmable Logic Array (PLA) to a
set of ten GPIO pins. Each pin must be configured to one of its
specific I/O function as described in Table 34.
GPIO
00
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.7
P2.0
UART
01
SIN
SOUT
RTS
CTS
RI
DCD
DSR
DTR
ECLK
CONV
Table 34: SPM configuration
UART/I
2
C/SPI
10
I2C0SCL
I2C0SDA
I2C1SCL
I2C1SDA
SPICLK
SPIMISO
SPIMOSI
SPICSL
SIN
SOUT
PLA
11
PLAI[0]
PLAI[1]
PLAI[2]
PLAI[3]
PLAI[4]
PLAI[5]
PLAI[6]
PLAO[0]
PLAO[4]
PLAO[5]
SPM0
SPM1
SPM2
SPM3
SPM4
SPM5
SPM6
SPM7
SPM8
SPM9
Table 34 details the mode for each of the SPMUX GPIO pins.
This configuration has to be done via
the GP0CON, GP1CON
and GP2CON MMRs. By default these ten pins are configured
as GPIOs.
UART SERIAL INTERFACE
The UART peripheral is a full-duplex Universal Asynchronous
Receiver/Transmitter, fully compatible with the 16450 serial
port standard. The UART performs serial-to-parallel conversion
on data characters received from a peripheral device or a
MODEM, and parallel-to-serial conversion on data characters
received from the CPU. The UART includes a fractional divider
for baudrate generation and has a network addressable mode.
The UART function is made available on the following 10 pins
of the ADuC702x:
Pin
SPM0 (mode 1)
SPM1 (mode 1)
SPM2 (mode 1)
SPM3 (mode 1)
SPM4 (mode 1)
SPM5 (mode 1)
SPM6 (mode 1)
SPM7 (mode 1)
SPM8 (mode 2)
SPM9 (mode 2)
Signal
RTS
CTS
SIN
SOUT
RI
DCD
DSR
DTR
SIN
SOUT
Table 35: UART signal description
Description
Request To Send
Clear To Send
Serial Receive Data
Serial Transmit Data
Ring Indicator
Data Carrier Detect
Data Set Ready
Data Terminal Ready
Serial Receive Data
Serial Transmit Data
The serial communication adopts a asynchronous protocol that
supports various word length, stop bits and parity generation
options selectable in the configuration register.
Baud rate generation
There is two way of generating the UART baudrate.
-
Normal 450 UART baudrate generation:
The baudrate is a divided version of the core clock using the
value in COMDIV0 and COMDIV1 MMRs (16-bit value, DL).
DL
MHz
×
×
2
Baudrate
CD
×
=
16
2
088
.
45
The following table gives some common baudrate values:
Baudrate
CD
DL
Actual
baudrate
% error
9600
19200
115200
9600
19200
115200
0
0
0
3
3
3
92h
49h
0Ch
12h
9h
1h
9651
19301
117417
9785
19569
88062
0.53%
0.53%
1.92%
1.92%
1.92%
23.55%
Table 36: baudrate using the normal baudrate generator
-
Using the fractional divider:
The fractional divider combined with the normal baudrate
generator allows the generating of a wider range of more
accurate baudrates.
Core Clock
/(M+N/2048)
/16DL
UART
FBEN
/2
Figure 26: baudrate generation options
Calculation of the baudrate using fractional divider is as follow:
)
2048
(
2
16
2
088
.
45
N
M
DL
MHz
Baudrate
CD
+
×
×
×
×
=
2
16
2
088
.
×
45
2048
×
×
×
=
+
DL
Baudrate
MHz
N
M
CD
Example:
Generation of 9600 baud with CD bits = 3. The previous table
gives DL = 12h.
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