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參數(shù)資料
| 型號： | ADUC702X |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 33/80頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC702X |
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Preliminary Technical Data
ADuC702x Series
FLASH/EE CONTROL INTERFACE
Rev. PrB | Page 33 of 80
Serial, parallel and JTAG programming use the Flash/EE
Control Interface, which includes seven MMRs:
-
FEESTA:
read only register, reflects the status of the Flash
Control Interface
-
FEEMOD:
sets the operating mode of the Flash Control
Interface
-
FEECON:
8-bit
command register. The commands are
described Table 14
-
FEEDAT:
16-bit data register.
-
FEEADR:
16-bit address register.
-
FEESIGN:
24-bit code signature
-
FEEPRO:
protection following subsequent reset MMR.
Requires software key. See description Table
15
-
FEEHIDE:
Immediate Protection MMR. Does not require
any software keys. See description Table 15
Table 12: FEESTA MMR bit designations
Bit
15-6
5
Description
Reserved
Burst command enable
Set
when the command is a burst command: 0x07, 0x08 or 0x09
Cleared
when other command
Reserved
Flash interrupt status bit
Set
automatically when an interrupt occurs, i.e. when a command is complete and the Flash/EE interrupt enable bit in the
FEEMOD register is set
Cleared
when reading FEESTA register
Flash/EE controller busy
Set
automatically when the controller is busy
Cleared
automatically when the controller is not busy
Command fail
Set
automatically when a command completes unsuccessfully
Cleared
automatically when reading FEESTA register
Command complete
Set
by MicroConverter when a command is complete
Cleared
automatically when reading FEESTA register
4
3
2
1
0
Table 13: FEEMOD MMR bit designations
Bit
7-5
4
Description
Reserved
Flash/EE interrupt enable:
Set
by user to enable the Flash/EE interrupt. The interrupt will occur when a command is complete.
Cleared
by user to disable the Flash/EE interrupt
Reserved
3-0
Table 14: command codes in FEECON
Code
0x00
*
0x01
*
0x02
*
0x03
*
command
Null
Single Read
Single Write
Erase-Write
Description
Idle state
Load FEEDAT with the 16-bit data indexed by FEEADR
Write FEEDAT at the address pointed by FEEADR. This operation takes 20
μ
s.
Erase the page indexed by FEEADR and write FEEDAT at the location pointed by FEEADR. This operation
takes 20ms
Compare the contents of the location pointed by FEEADR to the data in FEEDAT. The result of the
comparison is returned in FEESTA bit 1
Erase the page indexed by FEEADR
0x04
*
Single Verify
0x05
*
Single Erase
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