參數(shù)資料
型號： ADUC702
廠商： Analog Devices, Inc.
英文描述： 5 AMP MINIATURE POWER RELAY
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁數(shù)： 37/80頁
文件大小： 840K
代理商： ADUC702
Preliminary Technical Data
ADuC702x Series
OTHER ANALOG PERIPHERALS
DAC
The ADuC702x incorporate dual 12-bit voltage output DACs
on-chip. Each DAC has a rail-to-rail voltage output buffer
capable of driving 5k
/100pF. Each buffer can be bypassed.
Each DAC has three selectable ranges, 0V to V
REF
(internal
bandgap 2.5V reference), 0V to DAC
REF
(pin 56) and 0V to
AV
DD
. DAC
REF
is equivalent to an external reference for the
Rev. PrB | Page 37 of 80
DAC. The signal range is 0V to AV
DD
.
DAC MMRs interface
Each DAC is configurable independently through a Control
register and a Data register. These two registers are identical for
the four DACs and only DAC0CON and DAC0DAT will be
described in detail.
Table 19: DAC0CON MMR bit designations
Bit
6
Name
DACBYP
Description
Buffer bypass bit:
Set
by the user to bypass the output buffer.
Cleared
by user to buffer the DAC output. By default the DAC is buffered.
DAC update rate:
Set
by the user to update the DAC using timer1.
Cleared
by user to update the DAC using the core clock.
DAC clear bit:
Set
by the user to enable normal DAC operation.
Cleared
by user to reset data register of the DAC to zero.
Reserved
This bit should be left at ‘0’
Reserved
This bit should be left at ‘0’
DAC range bits
00
Power down mode. The DAC output is in tri-state
01
0-DAC
REF
range
10
0-V
REF
(2.5V) range
11
0-AV
DD
range
5
DACCLK
4
DACCLR
3
2
1-0
Table 20: DAC0DAT MMR bit designations
Bit
31-28
27-16
15-0
Description
Reserved
12-bit data for DAC0
Reserved
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