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| 型號(hào)： | ADUC702 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 AMP MINIATURE POWER RELAY |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁(yè)數(shù)： | 20/80頁(yè) |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC702 |
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ADuC702x Series
Preliminary Technical Data
-
Memory abort
-
Attempted execution of an undefined instruction
-
Software interrupt (SWI) instruction which can be used to
make a call to an operating system.
Rev. PrB | Page 20 of 80
Typically the programmer will define interrupts as IRQ but for
higher priority interrupt, i.e. faster response time, the
programmer can define interrupt as FIQ.
ARM Registers
ARM7TDMI has a total of 37 registers, of which 31 are general
purpose registers and six are status registers. Each operating
mode has dedicated banked registers.
When writing user-level programs, 15 general purpose 32-bit
registers (r0 to r14), the program counter (r15) and the current
program status register (CPSR) are usable. The remaining
registers are used only for system-level programming and for
exception handling.
When an exception occurs, some of the standard register are
replaced with registers specific to the exception mode. All
exception modes have replacement banked registers for the
stack pointer (r13) and the link register (r14) as represented in
Figure 3. The fast interrupt mode has more registers (8 to 12)
for fast interrupt processing, so that the interrupt processing
can begin without the need to save or restore these registers and
thus save critical time in the interrupt handling process.
user mode
fiq
mode
svc
mode
abort
mode
irq
mode
undefined
mode
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14
r15 (PC)
r8_fiq
r9_fiq
r10_fiq
r11_fiq
r12_fiq
r13_fiq
r14_fiq
r13_svc
r14_svc
r13_abt
r14_abt
r13_irq
r14_irq
r13_und
r14_und
usable in user mode
system modes only
CPSR
SPSR_fiq
SPSR_svc
SPSR_und
SPSR_abt
SPSR_irq
Figure 3: register organisation
More information relative to the programmer’s model and the
ARM7TDMI core architecture can be found in the following
documents from ARM:
- DDI0029G, ARM7TDMI Technical Reference Manual.
- DDI0100E, ARM Architecture Reference Manual.
Interrupt latency
The worst case latency for an FIQ consists of the longest time
the request can take to pass through the synchronizer, plus the
time for the longest instruction to complete (the longest
instruction is an LDM) which loads all the registers including
the PC, plus the time for the data abort entry, plus the time for
FIQ entry. At the end of this time, the ARM7TDMI will be
executing the instruction at 0x1C (FIQ interrupt vector
address). The maximum total time is 50 processor cycles, which
is just over 1.1
μ
S in a system using a continuous 45 MHz
processor clock. The maximum IRQ latency calculation is
similar, but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles
if the LDM command is not used, some compilers have an
option to compile without using this command. Another option
is to run the part in THUMB mode where this is reduced to 22
cycles.
The minimum latency for FIQ or IRQ interrupts is five cycles in
total which consists of the shortest time the request can take
through the synchronizer plus the time to enter the exception
mode.
Note that the ARM7TDMI will always be run in ARM (32-bit)
mode when in privileged modes, i.e. when executing interrupt
service routines.
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