參數(shù)資料
型號(hào)： ADUC702
廠商： Analog Devices, Inc.
英文描述： 5 AMP MINIATURE POWER RELAY
中文描述： 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器
文件頁(yè)數(shù)： 34/80頁(yè)
文件大?。?/td> 840K
代理商： ADUC702
ADuC702x Series
Preliminary Technical Data
0x06
*
Rev. PrB | Page 34 of 80
Mass erase
Erase 62kByte of user space. The 2kByte of kernel are protected. This operation takes 2.48s To prevent
accidental execution a command sequence is required to execute this instruction, this is described below.
Default command. No write is allowed. This operation takes 2 cycles
Write can handle a maximum of 8 data of 16 bits and takes a maximum of 8 x 20
μ
s
0x07
0x08
Burst read
Burst read-
write
Erase Burst
read-write
Burst
termination
Signature
0x09
Will automatically erase the page indexed by the write, allow to write pages without running an erase
command. This command takes 20 ms to erase the page + 20
μ
s per data to write
Stops the running burst to allow execution from Flash/EE immediately
0x0A
0x0B
Give a signature of the 64kBytes of Flash/EE in the 24-bit FEESIGN MMR. This operation takes 32778 clock
cycles.
This command can be run only once. The value of FEEPRO is saved and can be removed only with a mass
erase (0x06) or with the key
Reserved
Reserved
No operation, interrupt generated
*
The FEECON will always read 0x07 immediately after execution of any of these commands.
Command Sequence for executing a Mass Erase
0x0C
Protect
0x0D
0x0E
0x0F
Reserved
Reserved
Ping
FEEADR = 0x800; //Any address
FEECON=0x01; //Read command
while (!(FEESTA & 0x01)){} //Wait for read
FEECON=0x04; //Verify Command
FEEDAT=0x06; //Mass erase enable
FEECON=0x06; //Mass erase command
Table 15: FEEPRO and FEEHIDE MMR bit designations
Bit
31
Description
Read protection
Cleared
by user to protect all code
Set
by user to allow reading the code
Write protection for pages 123 to 120, for pages 119 to 116… and for pages 0 to 3
Cleared
by user to protect the pages in writing
Set
by user to allow writing the pages
EXECUTION TIME FROM SRAM AND
FLASH/EE
30-0
This chapter describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle as the
access time of the SRAM is 2ns and a clock cycle is 22ns
minimum. However, if the instruction involve reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM, or three cycle if the data is in Flash/EE, one
cycle to execute the instruction and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction, for example a
branch instruction will take one cycle to fetch but also two cycle
to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16-bit and access time for 16-bit
words is 22ns, execution from Flash/EE cannot be done in one
cycle as from SRAM when CD bit =0. Also some dead times are
needed before accessing data for any value of CD bits.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0 and in Thumb
mode, where instructions are 16 bits, one cycle is needed to
fetch any instruction.
Timing is identical in both mode when executing instructions
that involve using the Flash/EE for data memory. If the
instruction to be executed is a control flow instruction, an extra
cycle is needed to decode the new address of the program
counter and then four cycles are needed to fill the pipe-line. A
data processing instruction involving only core register doesn’t
require any extra clock cycle but if it involves data in Flash/EE,
an extra clock cycle is needed to decode the address of the data
and two cycles to get the 32-bit data from Flash/EE. An extra
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