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| 型號(hào)： | ADUC702 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 5 AMP MINIATURE POWER RELAY |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 29/80頁 |
| 文件大?。?/td> | 840K |
| 代理商： | ADUC702 |
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Preliminary Technical Data
ADuC702x Series
CONVERTER OPERATION
Rev. PrB | Page 29 of 80
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture is described below for the three different modes of
operation.
Differential mode
The ADuC702x contains a successive approximation ADC
based on two capacitive DACs. Figure 11 and Figure 12 show
simplified schematics of the ADC in acquisition and conversion
phase, respectively. The ADC is comprised of control logic, a
SAR, and two capacitive DACs. In Figure 11 (the acquisition
phase), SW3 is closed and SW1 and SW2 are in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
Cs
Cs
A
B
A
B
Channel+
Channel-
CAPACITIVE
DAC
CAPACITIVE
DAC
MUX
CONTROL
LOGIC
COMPARATOR
AIN0
AIN11
.
SW3
SW2
SW1
V
REF
Figure 11: ADC acquisition phase
When the ADC starts a conversion (Figure 12), SW3 will open
and SW1 and SW2 will move to Position B, causing the
comparator to become unbalanced. Both inputs are
disconnected once the conversion begins. The control logic and
the charge redistribution DACs are used to add and subtract
fixed amounts of charge from the sampling capacitor arrays to
bring the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC’s output code. The output
impedances of the sources driving the V
IN+
and V
IN–
pins must
be matched; otherwise, the two inputs will have different
settling times, resulting in errors.
Cs
Cs
A
B
A
B
VREF
Channel+
Channel-
CAPACITIVE
DAC
CAPACITIVE
DAC
MUX
CONTROL
LOGIC
COMPARATOR
AIN0
AIN11
.
SW3
SW2
SW1
Figure 12: ADC conversion phase
Pseudo-differential mode
In pseudo-differential mode, Channel- is linked to the VIN- pin
of the ADuC702x and SW2 switches between A (Channel-) and
B (VREF). VIN- pin must be connected to Ground or a low
voltage. The input signal on V
IN
+ can then vary from V
IN
- to
V
REF
+ V
IN
-. Note V
IN
- must be chosen so that V
REF
+ V
IN
- does
not exceed AV
DD
.
Cs
Cs
A
B
A
B
Channel+
Channel-
CAPACITIVE
DAC
CAPACITIVE
DAC
MUX
CONTROL
LOGIC
COMPARATOR
AIN0
AIN11
.
SW3
SW2
SW1
V
REF
VIN-
Figure 13: ADC in pseudo-differential mode
Single-ended mode
In Single-ended mode, SW2 is always connected internally to
ground. The VIN- pin can be floating. The input signal range on
V
IN
+ is 0V to V
REF
.
Cs
Cs
A
B
Channel+
Channel-
CAPACITIVE
DAC
CAPACITIVE
DAC
MUX
CONTROL
LOGIC
COMPARATOR
AIN0
AIN11
.
SW3
SW1
VIN-
Figure 14: ADC in single-ended mode
Analog Input Structure
Figure 15 shows the equivalent circuit of the analog input
structure of the ADC. The four diodes provides ESD protection
for the analog inputs. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. This would cause these diodes to become forward
biased and start conducting into the substrate. These diodes can
conduct up to 10 mA without causing irreversible damage to
the part.
The capacitors C1 in Figure 15 are typically 4 pF and can
primarily be attributed to pin capacitance. The resistors are
lumped components made up of the ON resistance of the
switches. The value of these resistors is typically about 100
The capacitors, C2, are the ADC’s sampling capacitors and
have a capacitance of 16 pF typically.
.
For AC applications, removing high-frequency components
from the analog input signal is recommended by the use of an
RC low-pass filter on the relevant analog input pins. In
applications where harmonic distortion and signal-to-noise
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