參數(shù)資料
型號(hào)： ADP5589CP-EVALZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 39/52頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL ADP5589ACPZ
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，GPIO 擴(kuò)展器
已用 IC / 零件： ADP5589
主要屬性： 19 個(gè)可配置的 I/O
次要屬性： I²C 接口
已供物品： 板
ADP5589
Data Sheet
Rev. B | Page 44 of 52
Bits
Name
R/W
Description
[2: 0]
LOGIC2_SEL[2:0]
R/W
Configures the digital mux for Logic Block 2.
000 = off/disable.
001 = AND2.
010 = OR2.
011 = XOR2.
100 = FF2.
101 = IN_LA2.
110 = IN_LB2.
111 = IN_LC2.
LOGIC_FF_CFG Register 0x46
Table 78. LOGIC_FF_CFG Bit Descriptions
Bits
Name
R/W
Description
[7: 4]
R/W
Reserved.
3
FF2_SET
R/W
0 = FF2 not set in Logic Block 2.
1 = set FF2 in Logic Block 2.
2
FF2_CLR
R/W
0 = FF2 not cleared in Logic Block 2.
1 = clear FF2 in Logic Block 2.
1
FF1_SET
R/W
0 = FF1 not set in Logic Block 1.
1 = set FF1 in Logic Block 1.
0
FF1_CLR
R/W
0 = FF1 not cleared in Logic Block 1.
1 = clear FF1 in Logic Block 1.
LOGIC_INT_EVENT_EN Register 0x47
Table 79. LOGIC_INT_EVENT_EN Bit Descriptions
Bits
Name
R/W
Description
[7: 6]
R/W
Reserved.
5
LY2_DBNC_DIS
R/W
0 = output of Logic Block 2 is debounced before entering the event/interrupt block.
1 = output of Logic Block 2 is not debounced before entering the event/interrupt block. Use
with caution because glitches may generate interrupts prematurely.
4
LOGIC2_EVENT_EN
R/W
0 = LY2 cannot generate interrupt.
1 = allow LY2 activity to generate events on the FIFO.
3
LOGIC2_INT_LEVEL
R/W
Configure the logic level of LY2 that generates an interrupt.
0 = LY2 is active low.
1 = LY2 is active high.
2
LY1_DBNC_DIS
R/W
0 = output of Logic Block 1 is debounced before entering the event/interrupt block.
1 = output of Logic Block 1 is not debounced before entering the event/interrupt block. Use
with caution because glitches may generate interrupts prematurely.
1
LOGIC1_EVENT_EN
R/W
0 = LY1 cannot generate interrupt.
1 = allow LY1 activity to generate events on the FIFO.
0
LOGIC1_INT_LEVEL
R/W
Configure the logic level of LY1 that generates an interrupt.
0 = LY1 is active low.
1 = LY1 is active high.
POLL_TIME_CFG Register 0x48
Table 80. POLL_TIME_CFG Bit Descriptions
Bits
Name
R/W
Description
[7: 2]
Reserved.
[1: 0]
KEY_POLL_TIME[1:0]
R/W
Configure time between consecutive scan cycles.
00 = 10 ms.
01 = 20 ms.
10 = 30 ms.
11 = 40 ms.
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