參數(shù)資料
型號(hào)： ADP1871ACPZ-0.3-R7
廠商： ANALOG DEVICES INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, PDSO10
封裝： 3 X 3 MM, ROHS COMPLIANT, LFCSP-10
文件頁(yè)數(shù)： 29/44頁(yè)
文件大?。?/td> 1958K
代理商： ADP1871ACPZ-0.3-R7
ADP1870/ADP1871
Rev. A | Page 29 of 44
)
(
)
(
)
(
)
(
BIAS
REG
total
SW
REG
IN
LOSS
DR
LDO
DISS
P
I
V
C
f
V
V
P
+
×
×
×
+
=
(4)
where:
P
DISS(LDO)
is the power dissipated through the pass device in the
LDO block across VIN and VREG.
C
total
is the C
GD
+ C
GS
of the external MOSFET.
V
REG
is the LDO output voltage and bias voltage.
V
IN
is the high voltage input.
I
BIAS
is the dc input bias current.
P
DR(LOSS)
is the MOSFET driver loss.
For example, if the external MOSFET characteristics are θ
JA
(10-lead MSOP) = 171.2°C/W, f
SW
= 300 kHz, I
BIAS
= 2 mA,
C
upperFET
= 3.3 nF, C
lowerFET
= 3.3 nF, V
DR
= 4.62 V and V
REG
= 5.0 V
then the power loss is
(
(
[
10
3
10
300
(
62
.
×
×
×
×
×
+
= 57.12 mW
(
)
(
)
(
×
×
×
=
= 55.6 mW
+
=
DR
LDO
DISS
TOTAL
DISS
P
P
P
)
[
V
]
)
]
))
002
.
0
10
3
10
300
(
0
))
002
.
62
+
.
9
3
9
3
)
×
(
+
×
×
×
×
×
=
+
+
+
×
=
BIAS
REG
lowerFET
SW
REG
BIAS
DR
upperFET
SW
DR
C
LOSS
DR
V
I
V
f
I
V
C
f
P
)
002
.
5
10
3
10
300
(
)
V
5
V
13
(
)
9
3
+
×
×
+
×
×
×
=
BIAS
REG
total
SW
REG
IN
LDO
DISS
P
I
V
C
f
V
V
mW
6
55
mW
13
.
77
)
(
)
(
)
(
+
=
= 132.73 mW
The rise in package temperature (for 10-lead MSOP) is
×
θ
=
LOSS
DR
JA
R
P
T
LOSS
mW
05
.
132
°C
2
171
)
(
×
=
= 22.7°C
Assuming a maximum ambient temperature environment of 85°C,
°C
85
°C
7
22
+
=
×
=
A
R
J
T
T
T
°C
72
.
107
=
which is below the maximum junction temperature of 125°C.
DESIGN EXAMPLE
The ADP1870/ADP1871 are easy to use, requiring only a few
design criteria. For example, the example outlined in this section
uses only four design criteria: V
OUT
= 1.8 V I
LOAD
= 15 A (pulsing),
V
IN
= 12 V (typical), and f
SW
= 300 kHz.
Input Capacitor
The maximum input voltage ripple is usually 1% of the
minimum input voltage (11.8 V × 0.01 = 120 mV).
V
RIPP
= 120 mV
V
MAX,RIPPLE
=
V
RIPP
(
I
LOAD,MAX
×
ESR
)
= 120 mV (15 A × 0.001) = 45 mV
I
C
mV
105
10
300
4
A
3
15
4
,
,
×
×
×
=
=
RIPPLE
MAX
SW
MAX
LOAD
V
IN,min
f
= 120 μF
Choose five 22 μF ceramic capacitors. The overall ESR of five
22 μF ceramic capacitors is less than 1 mΩ.
I
RMS
=
I
LOAD
/2 = 7.5 A
P
CIN
= (
I
RMS
)
2
×
ESR
= (7.5 A)
2
× 1 mΩ = 56.25 mW
Inductor
Determine inductor ripple current amplitude as follows:
I
I
≈
Δ
= 5 A
3
LOAD
L
so calculating for the inductor value
(
×
Δ
L
I
V
2
13
V
8
10
300
V
5
)
V
8
×
V
2
13
(
)
3
×
×
=
×
=
IN,MAX
OUT
SW
OUT
IN,MAX
V
V
f
V
V
L
= 1.03 μH
The inductor peak current is approximately
15 A + (5 A × 0.5) = 17.5 A
Therefore, an appropriate inductor selection is 1.0 μH with
DCR = 3.3 mΩ (Würth Elektronik 7443552100) from Table 8
with peak current handling of 20 A.
2
L
)
(
LOSS
DCR
P
= 0.003 × (15 A)
2
= 675 mW
Current Limit Programming
The valley current is approximately
15 A (5 A × 0.5) = 12.5 A
Assuming a lower-side MOSFET R
ON
of 4.5 mΩ and 13 A as
the valley current limit from Table 7 and Figure 71 indicates, a
programming resistor (RES) of 100 kΩ corresponds to an A
CS
of 24 V/V.
Choose a programmable resistor of R
RES
= 100 kΩ for a current-
sense gain of 24 V/V.
Output Capacitor
Assume that a load step of 15 A occurs at the output and no more
than 5% is allowed for the output to deviate from the steady state
operating point. In this case, the ADP1870’s advantage is that
because the frequency is pseudo-fixed, the converter is able to
respond quickly because of the immediate, though temporary,
increase in switching frequency.
Δ
V
DROOP
= 0.05 × 1.8 V = 90 mV
Assuming that the overall ESR of the output capacitor ranges
from 5 mΩ to 10 mΩ,
Δ
×
=
DROOP
SW
V
f
I
DCR
×
=
)
mV
90
(
10
300
A
15
3
×
2
)
(
2
×
×
=
Δ
×
LOAD
OUT
I
C
= 1.11 mF
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