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參數(shù)資料
| 型號： | ADP1871ACPZ-0.3-R7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, PDSO10 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, LFCSP-10 |
| 文件頁數(shù)： | 26/44頁 |
| 文件大?。?/td> | 1958K |
| 代理商： | ADP1871ACPZ-0.3-R7 |
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ADP1870/ADP1871
EFFICIENCY CONSIDERATIONS
One of the important criteria to consider in constructing a dc-to-dc
converter is efficiency. By definition, efficiency is the ratio of the
output power to the input power. For high power applications at
load currents up to 20 A, the following are important MOSFET
parameters that aid in the selection process:
V
GS (TH)
: the MOSFET threshold voltage applied between
the gate and the source
R
DS (ON)
: the MOSFET on resistance during channel
conduction
Q
G
: the total gate charge
C
N1
: the input capacitance of the upper-side switch
C
N2
: the input capacitance of the lower-side switch
Rev. A | Page 26 of 44
The following are the losses experienced through the external
component during normal switching operation:
Channel conduction loss (both of the MOSFETs)
MOSFET driver loss
MOSFET switching loss
Body diode conduction loss (lower-side MOSFET)
Inductor loss (copper and core loss)
Channel Conduction Loss
During normal operation, the bulk of the loss in efficiency is due
to the power dissipated through MOSFET channel conduction.
Power loss through the upper-side MOSFET is directly pro-
portional to the duty cycle (D) for each switching period, and
the power loss through the lower-side MOSFET is directly
proportional to 1 D for each switching period. The selection
of MOSFETs is governed by the amount of maximum dc load
current that the converter is expected to deliver. In particular,
the selection of the lower-side MOSFET is dictated by the
maximum load current because a typical high current application
employs duty cycles of less than 50%. Therefore, the lower-side
MOSFET is in the on state for most of the switching period.
[
N1(ON)
N1,N2(CL)
R
D
P
(
)
]
2
LOAD
1
N2(ON)
I
R
D
×
×
+
×
=
MOSFET Driver Loss
Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through the driver
during operation and the Q
GATE
parameter of the external MOSFETs.
(
(
[
REG
lowerFET
SW
REG
V
C
f
V
×
where:
C
upperFET
is the input gate capacitance of the upper-side MOSFET.
C
lowerFET
is the input gate capacitance of the lower-side MOSFET.
I
BIAS
is the dc current flowing into the upper- and lower-side drivers.
V
DR
is the driver bias voltage (that is, the low input voltage
(V
REG
) minus the rectifier drop (see Figure 81)).
V
REG
is the bias voltage.
f
SW
is the controller switching frequency (300 kHz, 600 kHz, and
1.0 MHz)
)
[
V
]
)
]
BIAS
BIAS
DR
upperFET
+
SW
DR
LOSS
DR
I
I
V
C
f
P
+
+
×
=
)
(
800
720
640
560
480
400
320
240
160
80
300
1000
900
800
700
600
500
SWITCHING FREQUENCY (kHz)
400
R
+125°C
+25°C
–40°C
V
REG
= 2.7V
V
REG
= 3.6V
V
REG
= 5.5V
0
Figure 81. Internal Rectifier Voltage Drop vs. Switching Frequency
Switching Loss
The SW node transitions due to the switching activities of the
upper- and lower-side MOSFETs. This causes removal and
replenishing of charge to and from the gate oxide layer of the
MOSFET, as well as to and from the parasitic capacitance
associated with the gate oxide edge overlap and the drain and
source terminals. The current that enters and exits these charge
paths presents additional loss during these transition times. This
loss can be approximately quantified by using the following
equation, which represents the time in which charge enters and
exits these capacitive regions:
t
SW-TRANS
=
R
GATE
×
C
TOTAL
where:
C
TOTAL
is the C
GD
+ C
GS
of the external MOSFET.
R
GATE
is the gate input resistance of the external MOSFET.
The ratio of this time constant to the period of one switching cycle
is the multiplying factor to be used in the following expression:
t
P
2
-
)
(
×
×
×
=
IN
LOAD
SW
TRANS
SW
LOSS
SW
V
I
t
or
2
)
(
×
×
×
×
×
=
IN
LOAD
TOTAL
GATE
SW
LOSS
SW
V
I
C
R
f
P
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADP1871ACPZ-1.0-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 10LFCSP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
| ADP1871ARMZ-0.3-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 10-MSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
| ADP1871ARMZ-0.6-R7 | 功能描述:IC REG CTRLR BUCK PWM CM 10-MSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
| ADP1871ARMZ-0V3-R7 | 制造商:Analog Devices 功能描述: |
| ADP1871ARMZ-0V6-R7 | 制造商:Analog Devices 功能描述: |
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