參數(shù)資料
型號(hào)： ADP1871ACPZ-0.3-R7
廠商： ANALOG DEVICES INC
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, PDSO10
封裝： 3 X 3 MM, ROHS COMPLIANT, LFCSP-10
文件頁數(shù)： 28/44頁
文件大小： 1958K
代理商： ADP1871ACPZ-0.3-R7
ADP1870/ADP1871
THERMAL CONSIDERATIONS
The ADP1870/ADP1871 are used for dc-to-dc, step down, high
current applications that have an on-board controller, an on-board
LDO, and on-board MOSFET drivers. Because applications may
require up to 20 A of load current delivery and be subjected to
high ambient temperature surroundings, the selection of external
upper- and lower-side MOSFETs must be associated with careful
thermal consideration to not exceed the maximum allowable
junction temperature of 125°C. To avoid permanent or irreparable
damage if the junction temperature reaches or exceeds 155°C, the
part enters thermal shutdown, turning off both external MOSFETs,
and does not reenable until the junction temperature cools to
140°C (see the On-Board Low Dropout Regulator section).
In addition, it is important to consider the thermal impedance
of the package. Because the ADP1870/ADP1871 employ an on-
board LDO, the ac current (fxCxV) consumed by the internal
drivers to drive the external MOSFETs adds another element of
power dissipation across the internal LDO. Equation 3 shows the
power dissipation calculations for the integrated drivers and for
the internal LDO.
Table 9 lists the thermal impedance for the ADP1870/ADP1871,
which are available in both 10-lead MSOP and 10-lead LFCSP
packages.
Rev. A | Page 28 of 44
Table 9. Thermal Impedance for 10-lead MSOP
Parameter
10-Lead MSOP θ
JA
2-Layer Board
4-Layer Board
10-Lead LFCSP θ
JA
4-Layer Board
Thermal Impedance
213.1°C/W
171.7°C/W
40°C/W
Figure 83 specifies the maximum allowable ambient temperature
that can surround the ADP1870/ADP1871 IC for a specified
high input voltage (V
IN
). Figure 83 illustrates the temperature
derating conditions for each available switching frequency for
low, typical, and high output setpoints for both the 10-lead
MSOP and LFCSP packages. All temperature derating criteria
are based on a maximum IC junction temperature of 125°C.
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
5.5
19.0
17.5
16.0
14.5
13.0
11.5
10.0
8.5
7.0
M
T
V
IN
(V)
V
OUT
= 0.8V
V
OUT
= 1.8V
V
OUT
= HIGH SETPOINT
600kHz
300kHz
1MHz
0
Figure 83. Ambient Temperature vs. V
IN
for 10-Lead MSOP (171°C/W),
4-Layer EVB, CIN = 4.3 nF (Upper-/Lower-Side MOSFET)
130
125
120
115
110
105
100
95
90
85
80
5.5
19.0
17.5
16.0
14.5
13.0
11.5
10.0
8.5
7.0
M
T
V
IN
(V)
V
OUT
= 0.8V
V
OUT
= 1.8V
V
OUT
= HIGH SETPOINT
600kHz
300kHz
1MHz
0
Figure 84. Ambient Temperature vs. V
IN
for 10-Lead LFCSP (40°C/W),
4-Layer EVB, CIN = 4.3 nF (Upper-/Lower-Side MOSFET)
The maximum junction temperature allowed for the ADP1870/
ADP1871 ICs is 125°C. This means that the sum of the ambient
temperature (T
A
) and the rise in package temperature (T
R
),
which is caused by the thermal impedance of the package and
the internal power dissipation, should not exceed 125°C, as
dictated by the following expression:
T
J
=
T
R
×
T
A
where:
T
A
is the ambient temperature.
T
J
is the maximum junction temperature.
T
R
is the rise in package temperature due to the power
dissipated from within.
The rise in package temperature is directly proportional to its
thermal impedance characteristics. The following equation
represents this proportionality relationship:
T
R
=
θ
JA
×
P
DR(LOSS)
where:
θ
JA
is the thermal resistance of the package from the junction to
the outside surface of the die, where it meets the surrounding air.
P
DR(LOSS)
is the overall power dissipated by the IC.
The bulk of the power dissipated is due to the gate capacitance
of the external MOSFETs and current running through the on-
board LDO. The power loss equations for the MOSFET drivers
and internal low dropout regulator (see the MOSFET Driver
Loss section in the Efficiency Consideration section) are:
P
DR(LOSS)
= [
V
DR
× (
f
SW
C
upperFET
V
DR
+
I
BIAS
)] +
[
V
REG
× (
f
SW
C
lowerFET
V
REG
+
I
BIAS
)]
where:
C
upperFET
is the input gate capacitance of the upper-side MOSFET.
C
lowerFET
is the input gate capacitance of the lower-side MOSFET.
I
BIAS
is the dc current (2 mA) flowing into the upper- and lower-
side drivers.
V
DR
is the driver bias voltage (the low input voltage (V
REG
)
minus the rectifier drop (see Figure 81)).
V
REG
is the LDO output/bias voltage.
(1)
(2)
(3)
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