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參數(shù)資料
| 型號(hào)： | ADN2811ACPZ-CML |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA REC W/AMP 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.66GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 托盤 |
ADN2811
Rev. B | Page 13 of 20
The ADN2811 can accept any of the following reference clock
frequencies: 19.44 MHz, 38.88 MHz, 77.76 MHz at LVTTL/
LVCMOS/LVPECL/LVDS levels, or 155.52 MHz at LVPECL/
LVDS levels via the REFCLKN/P inputs, independent of data
rate. The input buffer accepts any differential signal with a
peak-to-peak differential amplitude of greater than 100 mV
(e.g., LVPECL or LVDS) or a standard single-ended low voltage
TTL input, providing maximum system flexibility. The
appropriate division ratio can be selected using the REFSEL0/1
pins, according to Table 5. Phase noise and duty cycle of the
reference clock are not critical, and 100 ppm accuracy is
sufficient.
REFSEL must be tied to VCC when the REFCLKN/P inputs are
active, or tied to VEE when the oscillator is used. No connection
between the XO pin and REFCLK input is necessary (see
Figure 14, Figure 15, and Figure 16). Note that the crystal should
operate in series resonant mode, which renders it insensitive to
external parasitics. No trimming capacitors are required.
LOCK DETECTOR OPERATION
The lock detector monitors the frequency difference between
the VCO and the reference clock and deasserts the loss of lock
signal when the VCO is within 500 ppm of center frequency
(see Figure 17). This enables the phase loop, which pulls the
VCO frequency in the remaining amount and also acquires
phase lock. Once locked, if the input frequency error exceeds
1000 ppm (0.1%), the loss of lock signal is reasserted and
control returns to the frequency loop, which reacquires and
maintains a stable clock signal at the output.
Table 5. Reference Frequency Selection
REFSEL
REFSEL[1..0]
Applied Reference
Frequency (MHz)
1
00
19.44
1
01
38.88
1
10
77.76
1
11
155.52
0
XX
REFCLKP/N Inactive. Use 19.44 MHz
XTAL oscillator on Pins XO1, XO2 (Pull
REFCLKP to VCC).
The frequency loop requires a single external capacitor between
CF1 and CF2. The capacitor specification is given in Table 7.
Table 7. Recommended CF Capacitor Specification
Parameter
Value
Temperature Range
40°C to +85°C
Capacitance
>3.0 F
Leakage
<80 nA
Rating
>6.3 V
An on-chip oscillator to be used with an external crystal is also
provided as an alternative to using the REFCLKN/P inputs.
Details of the recommended crystal are given in Table 6.
Table 6. Required Crystal Specifications
Parameter
Value
Mode
Series Resonant
Frequency/Overall Stability
19.44 MHz ±100 ppm
Frequency Accuracy
±100 ppm
Temperature Stability
±100 ppm
Aging
±100 ppm
ESR
50 max
1000
500
0
500
1000
fVCO ERROR
(ppm)
LOL
1
03019-B
-017
Figure 17. Transfer Function of LOL
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| ADN2811ACPZ-CML-RL | 功能描述:IC CLK DATA REC SDH 2.66GHZ 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時(shí)間 PLL:是 主要用途:SONET/SDH，STM 輸入:CML 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.66GHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商器件封裝:48-LFCSP（7x7） 標(biāo)準(zhǔn)包裝:1 |
| ADN2812 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP | 制造商:Analog Devices 功能描述:IC CLOCK/DATA RECOVERY |
| ADN2812ACP-RL | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACP-RL7 | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
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