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參數(shù)資料
| 型號： | ADN2811ACPZ-CML |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 0K |
| 描述： | IC CLK/DATA REC W/AMP 48-LFCSP |
| 標準包裝： | 1 |
| 類型： | 時鐘和數(shù)據恢復（CDR），多路復用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.66GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 48-LFCSP |
| 包裝： | 托盤 |
ADN2811
Rev. B | Page 12 of 20
FUNCTIONAL DESCRIPTION
CLOCK AND DATA RECOVERY
The ADN2811 recovers clock and data from serial bit streams at
OC-48 as well as the 15/14 FEC rates. The data rate is selected
by the RATE input (see Table 4).
Table 4. Data Rate Selection
RATE
Data Rate
Frequency (MHz)
0
OC-48
2488.32
1
OC-48 FEC
2666.06
LIMITING AMPLIFIER
The limiting amplifier has differential inputs (PIN/NIN) that
are internally terminated with 50 to an on-chip voltage ref-
erence (VREF = 0.6 V typically). These inputs are normally
ac-coupled, although dc coupling is possible as long as the input
common-mode voltage remains above 0.4 V (see Figure 22,
Figure 23, and Figure 24). Input offset is factory trimmed to
achieve better than 4 mV typical sensitivity with minimal drift.
The limiting amplifier can be driven differentially or single-
ended.
SLICE ADJUST
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise by
applying a differential voltage input of ±0.8 V to SLICEP/N
inputs. If no adjustment of the slice level is needed, SLICEP/N
should be tied to VCC.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front end level signal detect circuit indicates when
the input signal level has fallen below a user adjustable
threshold. The threshold is set with a single external resistor
from Pin 1, THRADJ, to GND. The LOS comparator trip point
versus the resistor value is illustrated in Figure 4 (this is only
valid for SLICEP = SLICEN = VCC). If the input level to the
ADN2811 drops below the programmed LOS threshold,
SDOUT (Pin 45) indicates the loss of signal condition with a
Logic 1. The LOS response time is ~300 ns by design, but is
dominated by the RC time constant in ac-coupled applications.
If the LOS detector is used, the quantizer slice adjust pins must
both be tied to VCC. This is to avoid interaction with the LOS
threshold level.
Note that it is not expected to use both LOS and slice adjust at
the same time; systems with optical amplifiers need the slice
adjust to evade ASE. However, a loss of signal in an optical link
that uses optical amplifiers causes the optical amplifier output
to be full-scale noise. Under this condition, the LOS would not
detect the failure. In this case, the loss of lock signal indicates
the failure because the CDR circuitry is unable to lock onto a
signal that is full-scale noise.
REFERENCE CLOCK
There are three options for providing the reference frequency to
the ADN2811: differential clock, single-ended clock, or crystal
oscillator. See Figure 14, Figure 15, and Figure 16 for example
configurations.
100k
100k
BUFFER
ADN2811
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
VCC
REFSEL
03019-B
-014
Figure 14. Differential REFCLK Configuration
OUT
100k
100k
BUFFER
ADN2811
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
VCC
REFSEL
CLK
OSC
VCC
NC
03019-B
-015
Figure 15. Single-Ended REFCLK Configuration
100k
100k
BUFFER
ADN2811
VCC/2
REFCLKN
REFCLKP
CRYSTAL
OSCILLATOR
XO1
XO2
REFSEL
NC
19.44MHz
VCC
003019-B
-016
Figure 16. Crystal Oscillator Configuration
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2811ACPZ-CML-RL | 功能描述:IC CLK DATA REC SDH 2.66GHZ 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 PLL:是 主要用途:SONET/SDH，STM 輸入:CML 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.66GHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商器件封裝:48-LFCSP（7x7） 標準包裝:1 |
| ADN2812 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP | 制造商:Analog Devices 功能描述:IC CLOCK/DATA RECOVERY |
| ADN2812ACP-RL | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACP-RL7 | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
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