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參數(shù)資料
| 型號： | ADN2811ACPZ-CML |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA REC W/AMP 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.66GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 托盤 |
ADN2811
Rev. B | Page 18 of 20
DC-COUPLED APPLICATION
The inputs to the ADN2811 can also be dc-coupled. This may
be necessary in burst mode applications where there are long
periods of CIDs and baseline wander cannot be tolerated. If the
inputs to the ADN2811 are dc-coupled, care must be taken not
to violate the input range and common-mode level
requirements of the ADN2811 (see Figure 23, Figure 24, and
Figure 25). If dc-coupling is required and the output levels of
the TIA do not adhere to the levels shown in Figure 24 and
Figure 25, there needs to be level shifting and/or an attenuator
between the TIA outputs and the ADN2811 inputs.
LOL TOGGLING DURING LOSS OF INPUT DATA
If the input data stream is lost due to a break in the optical link
(or for any reason), the clock output from the ADN2811 stays
within 1000 ppm of the VCO center frequency as long as there
is a valid reference clock. The LOL pin toggles at a rate of
several kHz because the LOL pin toggles between a Logic 1 and
a Logic 0 while the frequency loop and phase loop swap control
of the VCO. The chain of events is as follows:
The ADN2811 is locked to the input data stream; LOL = 0.
The input data stream is lost due to a break in the link. The
VCO frequency drifts until the frequency error is greater
than 1000 ppm. LOL is asserted to a Logic 1 as control of
the VCO is passed back to the frequency loop.
The frequency loop pulls the VCO to within 500 ppm of its
center frequency. Control of the VCO is passed back to the
phase loop and LOL is deasserted to a Logic 0.
The phase loop tries to acquire, but there is no input data
present so the VCO frequency drifts.
The VCO frequency drifts until the frequency error is
greater than 1000 ppm. LOL is asserted to a Logic 1 as
control of the VCO is passed back to the frequency loop.
This process is repeated until a valid input data stream is
re-established.
50
50
ADN2811
0.1
F
NIN
PIN
50
TIA
VREF
VCC
50
03019-B
-023
Figure 23. ADN2811 with DC-Coupled Inputs
VCM = 0.4V MIN
(DC-COUPLED)
VSE = 5mV MIN
PIN
NIN
V p-p = PIN – NIN = 2
× V
SE = 10mV AT SENSITIVITY
INPUT (V)
03019-
B-
024
Figure 24. Minimum Allowed DC-Coupled Input Levels
INPUT (V)
PIN
NIN
VCM = 0.6V
(DC-COUPLED)
VSE = 1.2V MAX
V p-p = PIN – NIN = 2
× V
SE = 2.4V MAX
03019-
B-
025
Figure 25. Maximum Allowed DC-Coupled Input Levels
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| ADN2811ACPZ-CML-RL | 功能描述:IC CLK DATA REC SDH 2.66GHZ 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 PLL:是 主要用途:SONET/SDH，STM 輸入:CML 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.66GHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商器件封裝:48-LFCSP（7x7） 標(biāo)準(zhǔn)包裝:1 |
| ADN2812 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP | 制造商:Analog Devices 功能描述:IC CLOCK/DATA RECOVERY |
| ADN2812ACP-RL | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACP-RL7 | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
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