- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1989 > ADN2811ACPZ-CML (Analog Devices Inc)IC CLK/DATA REC W/AMP 48-LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADN2811ACPZ-CML |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 20/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK/DATA REC W/AMP 48-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | SONET/SDH，STM |
| 輸入： | CML |
| 輸出： | CML |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.66GHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 48-LFCSP |
| 包裝： | 托盤 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)當(dāng)前第20頁(yè)
ADN2811
Rev. B | Page 9 of 20
Jitter Tolerance
LOS RESPONSE TIME
Jitter tolerance is defined as the peak-to-peak amplitude of the
sinusoidal jitter applied on the input signal that causes a 1 dB
power penalty. This is a stress test that is intended to ensure no
additional penalty is incurred under the operating conditions
(see Figure 10). Figure 11 shows the typical OC-48 jitter
tolerance performance of the ADN2811.
The LOS response time is the delay between the removal of the
input signal and the indication of loss of signal (LOS) at
SDOUT. The LOS response time of the ADN2811 is 300 ns typ
when the inputs are dc-coupled. In practice, the time constant
of the ac-coupling at the quantizer input determines the LOS
response time.
SLOPE = –20dB/DECADE
f0
f1
f2
f3
f4
JITTER FREQUENCY (Hz)
15
1.5
0.15
IN
P
U
T
J
ITTE
R
AMP
L
IT
UDE
(UI
)
03019-B
-010
JITTER SPECIFICATIONS
The ADN2811 CDR is designed to achieve the best bit-error-
rate (BER) performance, and has exceeded the jitter generation,
transfer, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions measured in UI (unit
intervals), where 1 UI = 1 bit period. Jitter on the input data
can cause dynamic phase errors on the recovered clock
sampling edge. Jitter on the recovered clock causes jitter on the
retimed data.
Figure 10. SONET Jitter Tolerance Mask
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2811 performance with respect to those specifications.
MODULATION FREQUENCY (Hz)
10
1k
100k
10M
100
10
0.1
A
M
P
L
ITUDE
(UI
p
-p
)
1
100
10k
1M
1
ADN2811
OC-48 SONET MASK
03019-B
-011
Jitter Generation
Jitter generation specification limits the amount of jitter that
can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter has
a 12 kHz high-pass cutoff frequency with a roll-off of
20 dB/decade and a low-pass cutoff frequency of at least
20 MHz. The jitter generated should be less than 0.01 UI rms
and 0.1 UI p-p.
Jitter Transfer
Jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of jitter
on an input signal that can be transferred to the output signal
(see Figure 9).
SLOPE = –20dB/DECADE
JITTER FREQUENCY (kHz)
0.1
J
ITTE
R
GAIN
(dB)
fC
ACCEPTABLE
RANGE
03019-B
-009
Figure 11. OC-48 Jitter Tolerance Curve
Figure 9. Jitter Transfer Curve
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADN2812ACPZ-RL7 | IC CLOCK/DATA RECOVERY 32LFCSP |
| ADN2813ACPZ-500RL7 | IC CLK/DATA REC 1.25GBPS 32LFCSP |
| ADN2814ACPZ-500RL7 | IC CLK/DATA REC 675MBPS 32-LFCSP |
| ADN2815ACPZ | IC CLK/DATA REC 1.25GBPS 32LFCSP |
| ADN2816ACPZ-500RL7 | IC CLK/DATA REC 675MBPS 32-LFCSP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADN2811ACPZ-CML-RL | 功能描述:IC CLK DATA REC SDH 2.66GHZ 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購(gòu)買時(shí)間 PLL:是 主要用途:SONET/SDH，STM 輸入:CML 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:是/是 頻率 - 最大值:2.66GHz 電壓 - 電源:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應(yīng)商器件封裝:48-LFCSP（7x7） 標(biāo)準(zhǔn)包裝:1 |
| ADN2812 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp |
| ADN2812ACP | 制造商:Analog Devices 功能描述:IC CLOCK/DATA RECOVERY |
| ADN2812ACP-RL | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
| ADN2812ACP-RL7 | 制造商:Analog Devices 功能描述:Clock and Data Recovery 32-Pin LFCSP EP T/R |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。